Patents by Inventor Chang-Cheol Lee
Chang-Cheol Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134739Abstract: Disclosed herein are a method and an apparatus for storing blockchain data based on error correction code. The method for storing blockchain data based on error correction code includes dividing block data to be stored into multiple subblock datasets, generating parity datasets corresponding to the block data, and storing the subblock datasets and the parity datasets in proportion to storage capacities of the blockchain data storage nodes.Type: ApplicationFiled: October 17, 2023Publication date: April 25, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chang-Soo KIM, Myung-Cheol LEE
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Patent number: 8941245Abstract: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.Type: GrantFiled: June 26, 2012Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Cheol Lee, Hyun-Jun Kim, In-Young Lee, Ki-Kwon Jeong
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Publication number: 20130105988Abstract: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.Type: ApplicationFiled: June 26, 2012Publication date: May 2, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Cheol LEE, Hyun-Jun KIM, In-Young LEE, Ki-Kwon JEONG
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Patent number: 7374966Abstract: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker transfer unit for moving the picker vertically and horizontally. The method for manufacturing a semiconductor package using the same may allow easy and rapid stacking of semiconductor chips, thereby improving the productivity of semiconductor package manufacture. Further, a semiconductor chip having a relatively thick film is attached onto another semiconductor chip having a relatively thin film. The thicker semiconductor chip may protect the thinner semiconductor chip from faults such as chipping or warpage which may occur due to external shocks such as that caused by a picker, thereby improving the reliability of the package.Type: GrantFiled: September 25, 2006Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Ill Kim, Dong-Kuk Kim, Chang-Cheol Lee, Tae-Hoe Hwang, Jae-Young Hong
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Publication number: 20080026506Abstract: A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.Type: ApplicationFiled: October 5, 2007Publication date: January 31, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Kuk KIM, Chang-Cheol LEE
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Patent number: 7298032Abstract: A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.Type: GrantFiled: February 25, 2004Date of Patent: November 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Kuk Kim, Chang-Cheol Lee
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Publication number: 20070018295Abstract: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker transfer unit for moving the picker vertically and horizontally. The method for manufacturing a semiconductor package using the same may allow easy and rapid stacking of semiconductor chips, thereby improving the productivity of semiconductor package manufacture. Further, a semiconductor chip having a relatively thick film is attached onto another semiconductor chip having a relatively thin film. The thicker semiconductor chip may protect the thinner semiconductor chip from faults such as chipping or warpage which may occur due to external shocks such as that caused by a picker, thereby improving the reliability of the package.Type: ApplicationFiled: September 25, 2006Publication date: January 25, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Ill KIM, Dong-Kuk KIM, Chang-Cheol LEE, Tae-Hoe HWANG, Jae-Young HONG
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Patent number: 7148080Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.Type: GrantFiled: March 7, 2003Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Pyoung Wan Kim, Sang Hyeop Lee, Chang Cheol Lee, Gun Ah Lee
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Patent number: 7135353Abstract: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker transfer unit for moving the picker vertically and horizontally. The method for manufacturing a semiconductor package using the same may allow easy and rapid stacking of semiconductor chips, thereby improving the productivity of semiconductor package manufacture. Further, a semiconductor chip having a relatively thick film is attached onto another semiconductor chip having a relatively thin film. The thicker semiconductor chip may protect the thinner semiconductor chip from faults such as chipping or warpage which may occur due to external shocks such as that caused by a picker, thereby improving the reliability of the package.Type: GrantFiled: August 10, 2004Date of Patent: November 14, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Ill Kim, Dong-Kuk Kim, Chang-Cheol Lee, Tae-Hoe Hwang, Jae-Young Hong
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Patent number: 7096914Abstract: In an embodiment of the invention an apparatus is configured to stack a plurality of semiconductor chips having the same or similar size. The apparatus includes a tape providing unit for providing an insulating adhesive tape, a tape attaching device for attaching the insulating adhesive tape to an area between electrode pads of a first chip, and a chip attaching device for attaching a second chip to the insulating adhesive tape.Type: GrantFiled: July 29, 2003Date of Patent: August 29, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Kuk Kim, Min-Il Kim, Sang-Yeop Lee, Chang-Cheol Lee
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Publication number: 20060105477Abstract: In an embodiment of the invention, a device for manufacturing a wafer-level package includes a wafer sawing unit, a sorting unit, a pickup unit, and a placing unit. The wafer sawing unit cuts a wafer into wafer-level packages. The sorting unit performs a sorting process on the wafer-level packages to judge whether each of the wafer-level packages is normal or not. The pickup unit picks up the normal wafer-level packages. The placing unit stores the normal wafer-level packages in a storage case. The sawing process, the sorting process, and the placing process for the wafer-level package can be automatically performed within one device, thus a processing time reduction, a processing accuracy increase, and manpower reduction are achieved compared with the case where the processes are performed manually.Type: ApplicationFiled: November 15, 2005Publication date: May 18, 2006Inventors: Suk-Kun Lim, Chae-Hun Im, Min-Ill Kim, Chang-Cheol Lee
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Publication number: 20050054140Abstract: The present invention relates to an apparatus for stacking semiconductor chips, a method for manufacturing a semiconductor package using the same and a semiconductor package manufactured thereby. The apparatus for stacking semiconductor chips may comprise two tables for supporting wafers, a picker for picking up semiconductor chips and a picker transfer unit for moving the picker vertically and horizontally. The method for manufacturing a semiconductor package using the same may allow easy and rapid stacking of semiconductor chips, thereby improving the productivity of semiconductor package manufacture. Further, a semiconductor chip having a relatively thick film is attached onto another semiconductor chip having a relatively thin film. The thicker semiconductor chip may protect the thinner semiconductor chip from faults such as chipping or warpage which may occur due to external shocks such as that caused by a picker, thereby improving the reliability of the package.Type: ApplicationFiled: August 10, 2004Publication date: March 10, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Min-Ill Kim, Dong-Kuk Kim, Chang-Cheol Lee, Tae-Hoe Hwang, Jae-Young Hong
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Publication number: 20040201088Abstract: A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.Type: ApplicationFiled: February 25, 2004Publication date: October 14, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Kuk Kim, Chang-Cheol Lee
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Publication number: 20040031570Abstract: An apparatus for bonding a chip has means for providing a substrate including a first chip. The apparatus further includes a tape providing unit for providing an insulating adhesive tape, a tape attaching device for attaching the insulating adhesive tape to an area between the electrode pads of the first chip, and a chip attaching device for attaching a second chip to the insulating adhesive tape.Type: ApplicationFiled: July 29, 2003Publication date: February 19, 2004Inventors: Dong-Kuk Kim, Min-II Kim, Sang-Yeop Lee, Chang-Cheol Lee
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Publication number: 20040014257Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.Type: ApplicationFiled: March 7, 2003Publication date: January 22, 2004Inventors: Pyoung Wan Kim, Sang Hyeop Lee, Chang Cheol Lee, Gun Ah Lee
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Patent number: 6087722Abstract: A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips.Type: GrantFiled: April 14, 1999Date of Patent: July 11, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Kwan Jai Lee, Young Jae Song, Do Soo Jeong, Tae Je Cho, Suk Hong Chang, Chang Cheol Lee, Beung Seuck Song, Jong Hee Choi