Patents by Inventor Chang-Chien Wong
Chang-Chien Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240015958Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
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Patent number: 11825648Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.Type: GrantFiled: May 18, 2021Date of Patent: November 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
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Publication number: 20230247827Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.Type: ApplicationFiled: April 13, 2023Publication date: August 3, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chang-Chien Wong, Sheng-Yuan Hsueh, Ching-Hsiang Tseng, Chi-Horn Pai, Shih-Chieh Hsu
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Patent number: 11665891Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.Type: GrantFiled: May 7, 2021Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chang-Chien Wong, Sheng-Yuan Hsueh, Ching-Hsiang Tseng, Chi-Horn Pai, Shih-Chieh Hsu
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Publication number: 20220392905Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.Type: ApplicationFiled: June 30, 2021Publication date: December 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang, Chang-Chien Wong, Te-Wei Yeh, Sheng-Yuan Hsueh
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Publication number: 20220336479Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.Type: ApplicationFiled: May 18, 2021Publication date: October 20, 2022Applicant: United Microelectronics Corp.Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
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Publication number: 20220328503Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.Type: ApplicationFiled: May 7, 2021Publication date: October 13, 2022Inventors: Kuo-Hsing Lee, Chang-Chien Wong, Sheng-Yuan Hsueh, Ching-Hsiang Tseng, Chi-Horn Pai, Shih-Chieh Hsu
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Publication number: 20220302118Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.Type: ApplicationFiled: April 14, 2021Publication date: September 22, 2022Inventors: Kuo-Hsing Lee, Kun-Hsien Lee, Sheng-Yuan Hsueh, Chang-Chien Wong, Ching-Hsiang Tseng, Tsung-Hsun Wu, Chi-Horn Pai, Shih-Chieh Hsu
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Patent number: 11450670Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.Type: GrantFiled: April 14, 2021Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Kun-Hsien Lee, Sheng-Yuan Hsueh, Chang-Chien Wong, Ching-Hsiang Tseng, Tsung-Hsun Wu, Chi-Horn Pai, Shih-Chieh Hsu
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Patent number: 11322215Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.Type: GrantFiled: May 21, 2021Date of Patent: May 3, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pin Tsao, Tsung-Hsun Wu, Liang-Wei Chiu, Kuo-Hsing Lee, Sheng-Yuan Hsueh, Kun-Hsien Lee, Chang-Chien Wong
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Patent number: 8922328Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.Type: GrantFiled: August 16, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong
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Patent number: 8399318Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: May 10, 2012Date of Patent: March 19, 2013Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20130043972Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong
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Publication number: 20120286390Abstract: An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length.Type: ApplicationFiled: September 8, 2011Publication date: November 15, 2012Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong, Wai-Yi Lien
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Publication number: 20120228718Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Inventors: Yung-Chang LIN, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20120225524Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: May 10, 2012Publication date: September 6, 2012Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8227890Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: December 18, 2009Date of Patent: July 24, 2012Assignee: United Microelectronics CorporationInventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8071437Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: GrantFiled: November 19, 2009Date of Patent: December 6, 2011Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng
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Publication number: 20110147853Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20110117710Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng