Abstract: An apparatus and method for processing a paging in a WCDMA terminal realize a hardware device for checking whether or not there is a page by interpreting a PICH and an SCCPCH according to a DXR cycle. When a page is detected by this device, a digital base band unit (DBB) is turned on to analyze a PI (paging indicator) of the PICH and a MAC header of the SCCPCH. Therefore, there is no need to operate the DBB at every DXR cycle to check for a page, and thereby the processing loads of the DBB and power consumption of the WCDMA terminal can be reduced significantly.

Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

Abstract: A method and apparatus is provided for replacing defective storage cells within a memory device having twisted bit lines. If a defective storage cell is discovered, the row containing that storage cell can be re-mapped to the neighboring row or the memory array. Each successive neighboring row is also re-mapped to succeeding neighboring rows by incrementing or decrementing the row addresses. This will cause the addresses to essentially shift one address value toward the redundant set of rows, and one redundant row will be subsumed for every defective row within the array. Whenever an address is shifted across a twist region, the data of that address is purposely inverted in binary voltage value (i.e., converted from a binary 1 to a binary 0, and vice versa) to accommodate the twisting of the true and complementary bit line locations.

Abstract: A rotary compressor having a plurality of compression chambers and adapted to vary a compression capacity according to a direction of rotation of roller pistons within the compression chambers. A rotating shaft provided with a plurality of eccentric parts drives the roller pistons to compress refrigerant in the compression chambers by eccentric rotations of the eccentric parts. A reversible motor selectively rotates the rotating shaft in opposite directions, and a clutch engages the roller pistons such that the roller pistons perform a compressing action or an idle action according to a rotating direction of the rotating shaft, thus varying the compression capacity of the compressor according to a rotating direction of the rotating shaft. Thus, the compression capacity may be varied without using an inverter circuit.

Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: A rotary compressor having a plurality of compression chambers and adapted to vary a compression capacity according to a direction of rotation of roller pistons within the compression chambers. A rotating shaft provided with a plurality of eccentric parts drives the roller pistons to compress refrigerant in the compression chambers by eccentric rotations of the eccentric parts. A reversible motor selectively rotates the rotating shaft in opposite directions, and a clutch engages the roller pistons such that the roller pistons perform a compressing action or an idle action according to a rotating direction of the rotating shaft, thus varying the compression capacity of the compressor according to a rotating direction of the rotating shaft. Thus, the compression capacity may be varied without using an inverter circuit.

Abstract: An apparatus and method for processing a paging in a WCDMA terminal realize a hardware device for checking whether or not there is a page by interpreting a PICH and an SCCPCH according to a DXR cycle. When a page is detected by this device, a digital base band unit (DBB) is turned on to analyze a PI (paging indicator) of the PICH and a MAC header of the SCCPCH. Therefore, there is no need to operate the DBB at every DXR cycle to check for a page, and thereby the processing loads of the DBB and power consumption of the WCDMA terminal can be reduced significantly.

Abstract: The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.

Abstract: The present invention discloses a novel method and system for accessing a semiconductor device at multiple operating speeds. The novel method and system of the present invention allows access to a semiconductor device by a pipeline circuit in which modification of the pipeline circuitry is not required to achieve multiple operating speeds. An example of the invention may be the utilization of an internal clock to control internal pipeline which may allow adjustment of an effective operating speed of a semiconductor device.

Abstract: A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.

Abstract: The present invention relates to an plug-in type electric interconnecting system.

Abstract: A memory device including a plurality of memory cells, a plurality of bit lines, a plurality of bit line sense amplifiers, a plurality of column port gates, and a column decoder connected to a multiple of five column port gates. Each of the bit line sense amplifiers is connected to at least one of the bit lines and to at least one of the memory cells. Each of the column port gates is connected to at least one of the bit line sense amplifiers. The column decoder provides signals to the column port gates to which it is connected to select corresponding bit lines connected to the column port gates.

Abstract: A self-bootstrapping device for sufficiently bootstrapping a bias applied to the gate of a MOS transistor included in the decoder of a semiconductor memory device requiring a high integration degree so that the MOS transistor can transmit the potential from its drain to its source. The self-bootstrapping device includes a first NMOS transistor for a signal transmission, and a second NMOS transistor connected between the gate of the first NMOS transistor and an address decoder circuit, the second NMOS transistor being applied at its gate with a source voltage, wherein the second NMOS transistor comprises a first diffusion region formed at a required portion of a semiconductor substrate, a second diffusion region formed around the first diffusion region while being spaced apart from the first diffusion region by a desired distance, and a gate electrode formed on the semiconductor substrate between the first and second diffusion regions.

Abstract: Disclosed is a single-ended bit line structure of latched type, capable of sensing data at a high speed. The present invention decreasing the power consumption, by selectively separating the single-ended sense amplifier from the bit line and the reference voltage generator through the PMOS transistors at the same time the sensing operation starts. The single-ended bit line structure according to the present invention includes a reference voltage generator for generating a constant voltage, a latched-type sense amplifier and a switching unit for separating the latched-type sense amplifier from the reference voltage generator and a bit line at the same time the latched-type sense amplifier is enabled.

Abstract: A reference voltage generation circuit for a semiconductor memory device comprising a reference voltage generator for generating first and second reference voltages, the first and second reference voltages having the opposite response characteristics with respect to a variation in a temperature or a supply voltage, a start-up circuit for determining an initial condition of the reference voltage generator in response to the supply voltage to stabilize the operation of the reference voltage generator, and a voltage amplifier for compensating a target reference voltage for the temperature variation in response to the first and second reference voltages from the reference voltage generator so that the target reference voltage can always be constant in level. The first reference voltage has a positive response characteristic with respect to the temperature and the supply voltage and the second reference voltage has a negative response characteristic with respect to the temperature and the supply voltage.

Abstract: A semiconductor memory device comprising a plurality of memory cell arrays each of which includes a plurality of memory cells, a plurality of word lines connected to the memory cells for addressing them, a plurality of bit lines connected to the memory cells for transferring data from/to them, a first word line decoder connected to the word lines for activating them, and a bit line decoder connected to the bit lines for activating them. The semiconductor memory device further comprises a plurality of metal lines. Each of the metal lines is formed every four of the word lines and connected to the first word line decoder. The semiconductor memory device further comprises a plurality of second word line decoders. Each of the second word line decoders is connected to a corresponding one of the metal lines to address one of corresponding four of the word lines.