Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrode layers, and external electrodes disposed on the body and connected to the first and second internal electrode layers, respectively. The body includes an active portion in which the first and second internal electrode layers are alternately disposed with the dielectric layer interposed therebetween, a cover portion disposed on an upper portion and a lower portion of the active portion, and a side margin portion disposed on both sides of the active portion opposing each other. When a content of magnesium (Mg) included in the active portion is A1, a content of magnesium (Mg) included in the cover portion is C1, and a content of magnesium (Mg) included in the margin portion is M1, 0<A1<M1?C1 and A1/C1?0.60 are satisfied.

Abstract: A light emitting element includes: a light emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked along one direction; and an insulating film surrounding an outer surface of at least one of the first semiconductor layer, the active layer, and the second semiconductor layer. The insulating film including a zinc oxide (ZnO) thin film layer.

Abstract: A light-emitting element includes a first semiconductor layer doped to have a first polarity, a second semiconductor layer doped to have a second polarity different from the first polarity, a light-emitting layer disposed between the first and second semiconductor layers, a shell layer formed on side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, the shell layer including a divalent metal element, and an insulating film covering an outer surface of the shell layer and surrounding the side surface of the light-emitting layer.

Abstract: The disclosure relates to a permanent magnet actuator comprising: a stator iron core having a space therein-side, and having a first wall and a second wall opposing the first wall; a movable element moving reciprocally between the first wall and the second wall, along a moving axis which connects the first wall and the second wall inside the space; a first magnetomotive force supplying body and a second magnetomotive force supplying body disposed respectively on the first wall and the second wall, so as to supply a magnetomotive force to the movable element for the reciprocal movement thereof, wherein, at least one of the first magnetomotive force supplying body and the second magnetomotive force supplying body selectively produces a bidirectional magnetomotive force; a permanent magnet disposed between the first magnetomotive force supplying body and the second magnetomotive force supplying body, and providing a coercive force to the movable element for maintaining the state thereof; and a driving circuit co

Abstract: A wearable apparatus for measuring position and action of an arm includes: a main frame worn on an upper body of a user; and an arm motion-measuring unit connected to a side of the main frame, having a plurality of joints, and worn on an arm of a user, in which at least any one of the joints of the arm motion-measuring unit has a straight-motional degree of freedom. Accordingly, an instructor can conveniently move both arms in the apparatus, can precisely instruct a two-arm robot in motions of the instructor's arms, can reduce learning time of the robot, and can make the robot quickly and accurately learn the motions.

Abstract: A wearable apparatus for measuring position and action of an arm includes: a main frame worn on an upper body of a user; and an arm motion-measuring unit connected to a side of the main frame, having a plurality of joints, and worn on an arm of a user, in which at least any one of the joints of the arm motion-measuring unit has a straight-motional degree of freedom. Accordingly, an instructor can conveniently move both arms in the apparatus, can precisely instruct a two-arm robot in motions of the instructor's arms, can reduce learning time of the robot, and can make the robot quickly and accurately learn the motions.

Abstract: The disclosure relates to a permanent magnet actuator comprising: a stator iron core having a space therein-side, and having a first wall and a second wall opposing the first wall; a movable element moving reciprocally between the first wall and the second wall, along a moving axis which connects the first wall and the second wall inside the space; a first magnetomotive force supplying body and a second magnetomotive force supplying body disposed respectively on the first wall and the second wall, so as to supply a magnetomotive force to the movable element for the reciprocal movement thereof, wherein, at least one of the first magnetomotive force supplying body and the second magnetomotive force supplying body selectively produces a bidirectional magnetomotive force; a permanent magnet disposed between the first magnetomotive force supplying body and the second magnetomotive force supplying body, and providing a coercive force to the movable element for maintaining the state thereof; and a driving circuit co

Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.

Abstract: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.

Abstract: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.

Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.

Abstract: A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A semiconductor memory device stably performs a write operation with reduced current consumption. The semiconductor memory device includes a global data, a control unit, a termination resistor unit, and a storage unit. The global data line transmits data. The control unit generates a global control signal during a read operation or a write operation. The termination resistance unit supplies termination resistance to the global data line in response to the global control signal. The storage unit stores the data transmitted to the global data line while the termination resistance unit is inactivated. A method for driving the semiconductor memory device includes detecting a read operation or a write operation and supplying termination resistance when the read or write operation is detected.

Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.

Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.

Abstract: A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.