Patents by Inventor Chang-Jen Hsieh
Chang-Jen Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11785862Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.Type: GrantFiled: May 13, 2021Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Publication number: 20220352457Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate, in which the substrate has a cell region and a logic region adjacent to the cell region. A bottom electrode, a memory layer, and a top electrode are formed in sequence over the cell region of the substrate. A first spacer is formed extending upwards from the bottom electrode. A second spacer is formed extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Hung-Cho WANG, Sheng-Chang CHEN, Jun-Yao CHEN, Chang-Jen HSIEH
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Publication number: 20210280773Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.Type: ApplicationFiled: May 13, 2021Publication date: September 9, 2021Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Patent number: 11031543Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, a multi-layer stack is formed and patterned to form a hard mask, a top electrode and a resistance switching dielectric. Then, a first dielectric spacer layer is formed over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask. Then, a second dielectric spacer layer is formed directly on and conformally lining the first dielectric spacer layer. The first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.Type: GrantFiled: May 15, 2019Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Publication number: 20200127189Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, a multi-layer stack is formed and patterned to form a hard mask, a top electrode and a resistance switching dielectric. Then, a first dielectric spacer layer is formed over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask. Then, a second dielectric spacer layer is formed directly on and conformally lining the first dielectric spacer layer. The first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.Type: ApplicationFiled: May 15, 2019Publication date: April 23, 2020Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Patent number: 8809179Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.Type: GrantFiled: March 9, 2007Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Wei Wang, Derek Lin, Chen-Ming Huang, Chang-Jen Hsieh, Chi-Hsin Lo, Chung-Yi Yu, Feng-Jia Shiu, Yeur-Luen Tu, Yi-Shin Chu, Jen-Sheng Yang
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Patent number: 7951670Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.Type: GrantFiled: March 6, 2006Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ming Huang, Hung-Cheng Sung, Wen-Ting Chu, Chang-Jen Hsieh, Ya-Chen Kao
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Patent number: 7667261Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.Type: GrantFiled: April 17, 2007Date of Patent: February 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chang-Jen Hsieh, Hung-Cheng Sung, Wen-Ting Chu, Chen-Ming Huang, Ya-Chen Kao, Shih-Chang Liu, Chi-Hsin Lo, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 7652318Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.Type: GrantFiled: November 3, 2006Date of Patent: January 26, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Wen-Ting Chu, Chen-Ming Huang, Ya-Chen Kao, Shih-Chang Liu, Chi-Hsin Lo, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20080121975Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.Type: ApplicationFiled: November 3, 2006Publication date: May 29, 2008Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Wen-Ting Chu, Chen-Ming Huang, Ya-Chen Kao, Shih-Chang Liu, Chi-Hsin Lo, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20080105917Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.Type: ApplicationFiled: April 17, 2007Publication date: May 8, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Wen-Ting Chu, Chen-Ming Huang, Ya-Chen Kao, Shih-Chang Liu, Chi-Hsin Lo, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20070241386Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.Type: ApplicationFiled: March 9, 2007Publication date: October 18, 2007Inventors: Shih Wei Wang, Derek Lin, Chen-Ming Huang, Chang-Jen Hsieh, Chi-Hsin Lo, Chung-Yi Yu, Feng-Jia Shiu, Yeur-Luen Tu, Yi-Shin Chu, Jen-Sheng Yang
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Publication number: 20070205436Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.Type: ApplicationFiled: March 6, 2006Publication date: September 6, 2007Inventors: Chen-Ming Huang, Hung-Cheng Sung, Wen-Ting Chu, Chang-Jen Hsieh, Ya-Chen Kao
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Publication number: 20070181936Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.Type: ApplicationFiled: April 17, 2007Publication date: August 9, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Te-Hsun Hsu
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Patent number: 7226828Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.Type: GrantFiled: April 27, 2004Date of Patent: June 5, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Te-Hsun Hsu
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Publication number: 20050239247Abstract: A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.Type: ApplicationFiled: April 27, 2004Publication date: October 27, 2005Inventors: Chang-Jen Hsieh, Hung-Cheng Sung, Te-Hsun Hsu