Abstract: A display device includes subpixels on a substrate, position code patterns having a predetermined position code shape, when viewed in a plan view, each position code pattern being disposed at a region between at least two adjacent subpixels, and a pixel-defining layer defining a region where each subpixel is disposed and covering the position code patterns. The plurality of position code patterns are formed in a planar code shape and are configured to reflect light incident through the pixel-defining layer.

Abstract: A knee joint rehabilitation apparatus for a wheelchair includes a rehabilitation apparatus frame having a height corresponding to a length of each of legs of a patient sitting on the wheelchair; an upper leg support disposed at an upper end of the rehabilitation apparatus frame and supporting upper legs of the patient thereon while the patient is sitting on the wheelchair; a lower leg support pivotably connected to the upper leg support, wherein the lower legs of the patient are seated and supported on the lower leg support; and an exercise control unit disposed on the rehabilitation apparatus frame and configured to allow the lower leg support to pivot around a connection portion between the lower leg support and the upper leg support such that the patient performs rehabilitation exercise of the knee joint thereof while sitting on the wheelchair.

Abstract: A conductive composite material, a method of preparing the same, and a secondary battery including the same. The conductive composite material may increase the proportion of an active material when forming an electrode by chemically bonding a conductive material and a binder to each other. A method of preparing the conductive composite material comprises ionizing carbon-based particles in a predetermined polarity, ionizing PTFE particles in a polarity different from that of the carbon-based particles, and chemically bonding the ionized carbon-based particles and the ionized PTFE particles, which are ionized in different polarities, to each other.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: Disclosed is an exoskeleton-type rehabilitation robot system, including: a body part provided on a chair in which a user sits and provided with a robot arm capable of moving left or right based on the user seated on the chair; a conversion part configured to convert a position of the robot arm with respect to the body part; a driving part configured to articulate the robot arm with respect to the body part; and a controller configured to detect a change in a position of the robot arm and control a left or right driving mode of the driving part according to the position of the robot arm. In accordance with such a configuration, the exoskeleton-type rehabilitation robot system of the present invention is provided integrally with a chair, thereby having excellent space utilization. In addition, the user's initial preparation for rehabilitation training is simple, which can improve efficiency.

Abstract: In a non-contact pressure measurement system of a balloon catheter and a non-contact pressure measurement method of the balloon catheter using the same, the system includes a chamber part, a balloon, a tube part, a pump part and a displacement sensor. The chamber part stores a saline solution. The balloon is disposed inside of a body and is configured to be expanded with supply of the saline solution. The tube part is configured to connect the chamber part with the balloon. The pump part is configured to control the supply of the saline solution via the tube part. The displacement sensor is configured to measure an amount of the expansion of the tube part expanded with the supply of the saline solution, in a predetermined section of the tube part.

Abstract: High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

Abstract: A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

Abstract: A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

Abstract: High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

Abstract: A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

Abstract: A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.

Abstract: A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of the data unit for outputting data selected by a byte-operation, a sign extender controlled by the control signals for outputting the selected data and converting any non-selected data to a sign value, and a bus selection circuit controlled by the bus selection signals to select a bus among a plurality of buses and to load the selected bus with data outputted from the sign extender.

Abstract: A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of the data unit for outputting data selected by a byte-operation, a sign extender controlled by the control signals for outputting the selected data and converting any non-selected data to a sign value, and a bus selection circuit controlled by the bus selection signals to select a bus among a plurality of buses and to load the selected bus with data outputted from the sign extender.

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.