Abstract: A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: A hybrid output driver is disclosed that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: A hybrid output driver is disclosed that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, a computer readable tangible medium stores instructions executable by a computer. The instructions may be executable by the computer to determine whether a power detector circuit powered by a first voltage supply has received a test input from at least one voltage level-shifting device coupled to a second voltage supply.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract: In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed.

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract: In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, a computer readable tangible medium stores instructions executable by a computer. The instructions may be executable by the computer to determine whether a power detector circuit powered by a first voltage supply has received a test input from at least one voltage level-shifting device coupled to a second voltage supply.

Abstract: Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.