Patents by Inventor Chang Kuo-An

Chang Kuo-An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996842
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
  • Publication number: 20240165181
    Abstract: A composition for inhibiting intestinal permeability, treating leaky gut related diseases and/or preventing leaky gut related diseases including a Chinese herbal compound material or a Chinese herbal compound extract is provided. The Chinese herbal compound material includes Ganoderma, red jujube, longan and lotus seed. Moreover, the Chinese herbal compound extract includes a Ganoderma extract, a red jujube extract, a longan extract and a lotus seed extract.
    Type: Application
    Filed: June 1, 2023
    Publication date: May 23, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Hong PAN, Kuei-Chang LI, Zong-Keng KUO, Chu-Hsun LU, Yen-Wu HSIEH, Shu-Fang WEN
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11978715
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tsung Kuo, Hui-Chang Yu, Chih-Kung Huang, Wei-Teng Chang
  • Publication number: 20240142748
    Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Ying-Jen WANG, Ya-Hsiu WU, Chen-Chi KUO, Chao-Chang HU, Yi-Ho CHEN, Che-Wei CHANG, Ko-Lun CHAO, Sin-Jhong SONG
  • Patent number: 11973040
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Patent number: 11972113
    Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 30, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Bo-Chang Ye, Kuo-Cyuan Kuo, Chih-Chiang Chen
  • Publication number: 20240128039
    Abstract: An electromagnetic relay includes an electromagnetic unit, a magnetic moving subunit, a first conduct, a second conduct, a movable lead, and a movable contact. The movable lead has a swing portion and a resilient linkage portion. The movable contact is disposed on the swing portion. When the electromagnetic unit is energized, the magnetic moving subunit is attracted by the electromagnetic unit and pushes the resilient linkage portion of the movable lead such that the resilient linkage portion urges the swing portion to swing and that the movable contact disposed on the swing portion is urged to be in contact with one of the first contact and the second contact. When the electromagnetic unit is de-energized, the electromagnetic unit ceases to attract the magnetic moving subunit such that the movable contact is in contact with the other one of the first contact and the second contact.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 18, 2024
    Applicant: Excel Cell Electronic Co., Ltd.
    Inventor: Ming-Chang KUO
  • Publication number: 20240111935
    Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 4, 2024
    Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
  • Publication number: 20240108727
    Abstract: The present disclosure describes compositions including a eutectic matrix that includes methylsulfonylmethane and a sugar alcohol and particles of a nutraceutical in the eutectic matrix. In some embodiments, the sugar alcohol:methylsulfonylmethane ratio may be from 95:5 to 20:80. Also provided herein are methods for making the compositions and methods for increasing solubility and bioavailability of a nutraceutical.
    Type: Application
    Filed: December 2, 2021
    Publication date: April 4, 2024
    Applicant: InovoBiologic, Inc.
    Inventors: Roland Jacques Gahler, Simon Wood, Chuck Chang, Yun Chai Kuo
  • Patent number: 11942550
    Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240091216
    Abstract: Aqueous formulations of indacaterol are disclosed. The formulations may find use in the treatment of respiratory disorders, inflammatory disorders, or obstructive airway diseases. Methods of using the formulations and kits comprising the formulations are also encompassed by the disclosure.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 21, 2024
    Inventors: John CHAN, Keith Try UNG, Mei-Chang KUO, John Nigel Pritchard
  • Publication number: 20240088187
    Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 14, 2024
    Inventors: Chih Cheng Shih, Tsun-Kai Tsao, Jiech-Fun Lu, Hung-Wen Hsu, Bing Cheng You, Wen-Chang Kuo
  • Publication number: 20240083981
    Abstract: The present invention relates to the treatment of herpes simplex virus (HSV) infection using an anti-HSV antibody. In particular, the anti-HSV antibody specifically binds to the glycoprotein D (gD) of herpes simplex virus-1 (HSV-1) and herpes simplex virus-2 (HSV-2). The treatment of the present invention is effective against drug-resistant and/or recurrent HSV infection.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Applicant: United BioPharma, Inc.
    Inventors: Be-Sheng KUO, Chao-Hung LI, Hsiao-Yun SHAO, Yaw-Jen LIU, Shugene LYNN, Chang Yi WANG
  • Publication number: 20240063158
    Abstract: A method of making a semiconductor structure includes forming a first contact pad over an interconnect structure. The method further includes forming a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The method further includes depositing a first buffer layer over the interconnect structure, wherein the first buffer layer partially covers the second contact pad, and an edge of the second contact pad extends beyond the first buffer layer.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Gulbagh SINGH, Chih-Ming LEE, Chi-Yen LIN, Wen-Chang KUO, C. C. LIU
  • Patent number: 11908878
    Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Patent number: 11901387
    Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Publication number: 20240030261
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.
    Type: Application
    Filed: January 5, 2023
    Publication date: January 25, 2024
    Inventors: Wen-I Hsu, Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Wen-Chang Kuo
  • Patent number: D1014960
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 20, 2024
    Assignee: Voila Pooch
    Inventors: Hoyt Yang, Steven Hsing-Chang Kuo