Patents by Inventor Chang-Mao Wang
Chang-Mao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402288Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.Type: ApplicationFiled: July 4, 2022Publication date: December 14, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yeh-Sheng Lin, Chang-Mao Wang, Chun-Chi Yu, Chung-Yi Chiu
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Publication number: 20230152714Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Inventors: Hsin-Yu HSIEH, Kuan-Ying LAI, Chang-Mao WANG, Chien-Hao CHEN, Chun-Chi YU
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Publication number: 20220392768Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: United Microelectronics Corp.Inventors: Yi Jing Wang, Chia-Chang Hsu, Chien-Hao Chen, Chang-Mao Wang, Chun-Chi Yu
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Publication number: 20220367192Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.Type: ApplicationFiled: June 3, 2021Publication date: November 17, 2022Inventors: Kuan-Ying Lai, Hsin-Yu Hsieh, Chang-Mao Wang, Chung-Yi Chiu
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Patent number: 11488829Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.Type: GrantFiled: June 3, 2021Date of Patent: November 1, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Ying Lai, Hsin-Yu Hsieh, Chang-Mao Wang, Chung-Yi Chiu
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Patent number: 10777420Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.Type: GrantFiled: February 26, 2019Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
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Publication number: 20200273714Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.Type: ApplicationFiled: February 26, 2019Publication date: August 27, 2020Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
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Patent number: 9304389Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.Type: GrantFiled: October 31, 2013Date of Patent: April 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang
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Publication number: 20150118602Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang
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Patent number: 8954919Abstract: A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.Type: GrantFiled: November 1, 2013Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang, Yu-Chin Huang
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Patent number: 8785115Abstract: A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.Type: GrantFiled: February 9, 2012Date of Patent: July 22, 2014Assignee: United Microelectronics Corp.Inventors: Hung-Yi Wu, Yuan-Chi Pai, Yu-Wei Cheng, Chang-Mao Wang
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Publication number: 20130210237Abstract: A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: United Microelectronics Corp.Inventors: Hung-Yi Wu, Yuan-Chi Pai, Yu-Wei Cheng, Chang-Mao Wang