Patents by Inventor Chang-Ming Lu
Chang-Ming Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224238Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.Type: GrantFiled: September 16, 2016Date of Patent: March 5, 2019Assignee: Apple Inc.Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng
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Publication number: 20170294499Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.Type: ApplicationFiled: September 16, 2016Publication date: October 12, 2017Inventors: Chang Ming Lu, Chia-Yu Chen, Chih Pang Chang, Ching-Sang Chuang, Hung-Che Ting, Jung Yen Huang, Sheng Hui Shen, Shih Chang Chang, Tsung-Hsiang Shih, Yu-Wen Liu, Yu Hung Chen, Kai-Chieh Wu, Lun Tsai, Takahide Ishii, Chung-Wang Lee, Hsing-Chuan Wang, Chin Wei Hsu, Fu-Yu Teng
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Patent number: 9117915Abstract: A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.Type: GrantFiled: November 23, 2011Date of Patent: August 25, 2015Assignee: Au Optronics CorporationInventors: Chang-Ming Lu, Lun Tsai, Chia-Yu Chen
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Publication number: 20130043464Abstract: A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.Type: ApplicationFiled: November 23, 2011Publication date: February 21, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chang-Ming Lu, Lun Tsai, Chia-Yu Chen
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Patent number: 8334549Abstract: A light emitting diode and a fabricating method thereof are provided. A first-type semiconductor layer, a light emitting layer and a second-type semiconductor layer with a first surface are sequentially formed a substrate. Next, the first surface is treated during a surface treatment process to form a current-blocking region which extends from the first surface to the light emitting layer to a depth of 1000 angstroms. Afterward, a first electrode is formed above the current-blocking region of the second-type semiconductor layer, and a second electrode is formed to electrically contact to the first-type semiconductor layer. Since the current-blocking region is formed with a determined depth within the second-type semiconductor layer, the light extraction efficiency of the light emitting diode may be increased.Type: GrantFiled: February 17, 2011Date of Patent: December 18, 2012Assignee: Lextar Electronics CorporationInventors: Mong-Ea Lin, Yao-Hui Lin, Chao-Ming Chiu, Chang-Ming Lu
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Publication number: 20120037952Abstract: A light emitting diode and a fabricating method thereof are provided. A first-type semiconductor layer, a light emitting layer and a second-type semiconductor layer with a first surface are sequentially formed a substrate. Next, the first surface is treated during a surface treatment process to form a current-blocking region which extends from the first surface to the light emitting layer to a depth of 1000 angstroms. Afterward, a first electrode is formed above the current-blocking region of the second-type semiconductor layer, and a second electrode is formed to electrically contact to the first-type semiconductor layer. Since the current-blocking region is formed with a determined depth within the second-type semiconductor layer, the light extraction efficiency of the light emitting diode may be increased.Type: ApplicationFiled: February 17, 2011Publication date: February 16, 2012Applicant: Lextar Electronics CorporationInventors: Mong-Ea Lin, Yao-Hui Lin, Chao-Ming Chiu, Chang-Ming Lu
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Publication number: 20100221494Abstract: A method for forming a semiconductor layer includes following steps. First, an epitaxial substrate having at least a first growth region and at least a second growth region is provided. An area ratio of C plane to R plane in the first growth region is greater than 52/48. An epitaxial process is then performed on the epitaxial substrate to form a semiconductor layer. During the epitaxial process, a semiconductor material is selectively grown on the first growth region, and then the semiconductor material is laterally overgrown on the second growth region and covers the same.Type: ApplicationFiled: May 14, 2009Publication date: September 2, 2010Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chang-Ming Lu, Chih-Wei Chao, Te-Chung Wang, Kuo-Lung Fang, Chun-Jong Chang
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Patent number: 6100573Abstract: The invention provides a structure of a bonding pad, which comprising: a substrate; a dielectric layer formed over the substrate; a first metal layer formed in the dielectric layer; a second metal layer formed in the dielectric layer and above the first metal layer; a plurality of first plugs formed between the first metal layer and the second metal layer, wherein the plugs are used for connecting the first metal layer with the second metal layer; a third metal layer formed over the dielectric layer; and a plurality of second plugs, formed between the second metal layer and the third metal layer, wherein the second plugs are used for connecting the second metal layer with the third metal layer.Type: GrantFiled: August 19, 1998Date of Patent: August 8, 2000Assignee: United Integrated Circuits Corp.Inventors: Chang-Ming Lu, Shu-Ying Lu
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Patent number: 6030872Abstract: A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.Type: GrantFiled: February 1, 1999Date of Patent: February 29, 2000Assignee: United Integrated Circuits Corp.Inventors: Jau-Hone Lu, Shu-Ying Lu, Chang-Ming Lu, Ya-Ling Hung