Patents by Inventor Chang-Sheng Lin

Chang-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220187559
    Abstract: An optical fiber routing assembly for interfacing with co-package optical (CPO) modules is disclosed. The optical fiber routing assembly includes a housing, a plurality of terminated optical fibers routed within the housing, a first set of adapters, and a second set of adapters. The first set of adapters is arranged vertically on an upper panel of the housing and facilitates connecting the plurality of terminated optical fibers to the CPO modules via terminated jumper optical fibers. The second set of adapters is arranged horizontally and configured to facilitate connecting the plurality of terminated optical fibers to one or more electronic systems. A combination of the first set of adapters and the second set of adapters facilitates communication between the CPO modules and the electronic systems. The optical fiber routing assembly provides fiber management to alleviate maintenance or heat issues associated with dense fiber routing around electronic components.
    Type: Application
    Filed: May 25, 2021
    Publication date: June 16, 2022
    Inventors: Chang-Sheng Lin, Zong-Syun He, Hsiao-Hsien Weng, Rong-Teng Sie
  • Publication number: 20220149170
    Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Patent number: 11312882
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 11309201
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 19, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Publication number: 20220115832
    Abstract: A system and method for safe use of an optics assembly with an external light source and an optically coupled optics module is disclosed. The system includes an external light module emitting a continuous wave laser through an output port. An optics module has an input port and a memory. The optics module generates a modulated optical signal. The memory stores the power level of the continuous wave laser signal received by the optics module. An optical jumper is provided for coupling the output port with the input port. A communication bus is coupled between a controller and the external light source module. The controller sets the external light source at a low power level and transitions the external light source to a high power level when the stored power level of the continuous wave laser signal received by the optics module exceeds a predetermined level.
    Type: Application
    Filed: January 21, 2021
    Publication date: April 14, 2022
    Inventors: Chang-Sheng LIN, Hsiao-Hsien WENG, Zong-Syun HE
  • Publication number: 20210358786
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Publication number: 20210245344
    Abstract: A pneumatic electric nail gun includes a muzzle unit, a striking cylinder that is connected to the muzzle unit, a piston rod subunit that extends movably from the striking cylinder into the muzzle unit, an electric unit that drives movement of the piston rod subunit from a standby position to a nail-striking position for striking a nail, and a connecting unit that includes a plurality of fasteners and a plurality of buffer members. The fasteners extend through the electric unit and secure the electric unit to the muzzle unit. Each of the buffer members surrounds a respective one of the fasteners and fills a space between the respective one of the fasteners, the electric unit and the muzzle unit for shock absorption during a nail-striking process.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 12, 2021
    Applicant: BASSO INDUSTRY CORP.
    Inventors: An-Gi LIU, Chang-Sheng LIN, Fu-Ying HUANG
  • Patent number: 11011385
    Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
  • Patent number: 10916473
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20200407594
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 10774241
    Abstract: A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (H2O2), ammonium persulfate ((NH4)2S2O8), peroxymonosulfuric acid (H2SO5), ozone (O3) in de-ionized water, and sulfuric acid (H2SO4).
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Kuo-Yin Lin, Wen-Kuei Liu, Teng-Chun Tsai, Shen-Nan Lee, Kuo-Cheng Lien, Chang-Sheng Lin, Yu-Wei Chou
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 10734254
    Abstract: A method of processing a wafer is disclosed. The method includes, in some embodiments, causing a relative movement between a cleaning brush and a wafer. During the relative movement, a planar cleaning surface of the cleaning brush is brought into contact with a surface of the wafer to remove contaminants from the surface of the wafer. A first size of the cleaning brush, in a plan view, is larger than a second size of the wafer in the plan view.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
  • Patent number: 10596963
    Abstract: A fatigue alarm apparatus having a fatigue detector, a control unit and a stimulus alarm generator is illustrated. The fatigue detector detects whether a driver is drowsy. The control unit is electrically connected to the fatigue detector and the stimulus alarm generator. When the fatigue detector detects that the driver is drowsy, the stimulus alarm generator controlled by the control unit to generate two stimulus alarms having a rest time period therebetween, and then, after an interval period elapses, the control unit determines whether an alarming procedure of generating the two stimulus alarms is to be interrupted or repeated, wherein the rest time period is less than the interval period.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 24, 2020
    Assignee: LATTICE ENERGY TECHNOLOGY CORPORATION
    Inventors: Ta-Yi Chien, Pai-Hsiang Cheng, Ying-Ju Lai, Chang-Sheng Lin, Yung-Chou Chen, Guan-Hua Chen, Hsiang-Fu Fan, Yu-Kai Lin, Wen-Jing Xie
  • Publication number: 20200066580
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Tai-Yen PENG, Chang-Sheng LIN, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH
  • Publication number: 20200051855
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20200027760
    Abstract: The present disclosure, in some embodiments, relates to a brush cleaning apparatus. The brush cleaning apparatus includes a wafer support configured to support a wafer. The brush cleaning apparatus also includes a cleaning brush including a porous material coupled to a core material. An uppermost surface of the porous material defines a planar cleaning surface. A first nozzle is configured to apply a first cleaning liquid directly between the wafer and the planar cleaning surface of the cleaning brush.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
  • Patent number: 10510594
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Patent number: 10504753
    Abstract: A brush cleaning apparatus includes a wafer support configured to support a wafer, and at least one cleaning brush moveable relative to the wafer support. The at least one cleaning brush has opposite first and second sides, and, on the first side, a planar cleaning surface configured to come into contact with the wafer supported by the wafer support to remove contaminants from the wafer.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Sheng Lin, Hsin-Hsien Lu
  • Publication number: 20190358767
    Abstract: Some embodiments relate to a carrier head. The carrier head includes a housing configured to enclose a wafer, wherein the housing includes a retaining ring recess configured to circumferentially surround the wafer. A retaining ring, which includes a first ring-shaped layer and a second ring-shaped layer, is disposed in the retaining ring recess. The second ring-shaped layer is disposed deeper in the retaining ring recess than the first ring-shaped layer and separates the first ring-shaped layer from a bottom of the retaining ring recess. A hardness of the second ring-shaped layer is less than a hardness of the first ring-shaped layer.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 28, 2019
    Inventors: Chang-Sheng Lin, Hsin-Hsien Lu