Patents by Inventor Chang-Ting Chen
Chang-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135990Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 11966241Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.Type: GrantFiled: February 11, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
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Publication number: 20240124292Abstract: An auxiliary operation device for a droplet dispenser includes a droplet sensor, an imaging device and a processor. The droplet sensor has a detected area located between a droplet dispenser and a target area, wherein the droplet sensor detects a droplet output from the droplet dispenser, and outputs a corresponding droplet detection signal. The imaging device captures an image of the target area. The processor obtains a dripping time point at which the droplet passes through the detected area according to the droplet detection signal, and determines whether the target area is shielded within a first time range according to the image, so as to evaluate whether the droplet has successfully dropped into the target area. The above-mentioned auxiliary operating device of the droplet dispenser can objectively determine whether the droplets successfully drops into the target area, and improve the accuracy of judgment.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: SHAO HUNG HUANG, CHAO-TING CHEN, FONG HAO KUO, CHI-YUAN KANG, Chang Mu WU
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Publication number: 20220380779Abstract: Provided herein are systems and methods for the production of malonic acid or a salt thereof in recombinant host cells.Type: ApplicationFiled: August 31, 2020Publication date: December 1, 2022Inventors: Jeffrey DIETRICH, Andrew CONLEY, Christine CARLE, Nathan MIH, Chang-ting CHEN, Shuchi DESAI, Ee-been GOH, Poh TENG
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Publication number: 20220283738Abstract: A flash memory and a writing method thereof are provided. The flash memory includes a plurality of memory blocks and a plurality of multiplex circuits. The memory blocks are arranged into a plurality of memory banks. Each of the memory blocks transmits a plurality of erase voltages or a plurality of program voltages to the corresponding memory bank for executing an erase operation or a program operation. The program operation is executed by one of the memory banks while the erase operation is executed by another one of the memory banks according to a programming while erasing instruction.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Chun-Lien Su, Chang-Ting Chen
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Patent number: 9652228Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.Type: GrantFiled: April 2, 2015Date of Patent: May 16, 2017Assignee: Macronix International Co., Ltd.Inventors: Kuen-Long Chang, Ken-Hui Chen, Chang-Ting Chen
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Patent number: 9489007Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.Type: GrantFiled: July 31, 2014Date of Patent: November 8, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Kuen-Long Chang, Ken-Hui Chen, Chang-Ting Chen
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Patent number: 9368220Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.Type: GrantFiled: August 4, 2014Date of Patent: June 14, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
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Publication number: 20150293556Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.Type: ApplicationFiled: July 31, 2014Publication date: October 15, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: KUEN-LONG CHANG, KEN-HUI CHEN, CHANG-TING CHEN
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Publication number: 20150286405Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.Type: ApplicationFiled: April 2, 2015Publication date: October 8, 2015Inventors: Kuen-Long CHANG, Ken-Hui CHEN, Chang-Ting CHEN
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Publication number: 20140376311Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.Type: ApplicationFiled: August 4, 2014Publication date: December 25, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
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Patent number: 8797802Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.Type: GrantFiled: June 28, 2012Date of Patent: August 5, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
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Patent number: 8723559Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.Type: GrantFiled: September 5, 2012Date of Patent: May 13, 2014Assignee: Macronix International Co., Ltd.Inventors: Chang-Ting Chen, Chin-Hung Chang, Shang-Chi Yang, Kuan-Ming Lu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Publication number: 20140062543Abstract: A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Applicant: Macronix International Co., Ltd.Inventors: Chang-Ting Chen, Chin-Hung Chang, Shang-Chi Yang, Kuan-Ming Lu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: 8638618Abstract: An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.Type: GrantFiled: July 19, 2011Date of Patent: January 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Shuo-Nan Hung, Chang Ting Chen, Chi-Yu Hung, Tseng-Yi Liu
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Publication number: 20130242665Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.Type: ApplicationFiled: June 28, 2012Publication date: September 19, 2013Applicant: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
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Publication number: 20120163087Abstract: An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.Type: ApplicationFiled: July 19, 2011Publication date: June 28, 2012Applicant: Macronix International Co., Ltd.Inventors: Shuo-Nan Hung, Chang Ting Chen, Chi-Yu Hung, Tseng-Yi Liu
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Patent number: 7692960Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.Type: GrantFiled: December 20, 2006Date of Patent: April 6, 2010Assignee: Macronix International Co., Ltd.Inventors: Chang-Ting Chen, Chun-Jen Huang
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Publication number: 20080159060Abstract: A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Inventors: Chang-Ting Chen, Chung-Kuang Chen