Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: The present invention relates to the fields of heat storage and thermally conductive materials, and discloses a highly thermally conductive heat storage material, a preparation method therefor, and the application thereof, and a composition for preparing a highly thermally conductive heat storage material and the application thereof. The highly thermally conductive heat storage material comprises 11-41 wt % of a carbonaceous part and 59-89 wt % of a graphitic part; for the carbonaceous part, Lc>18 nm, La>35 nm, d002<0.3388 nm, and the degree of graphitization is 60% to 95%; for the graphitic part, Lc>50 nm; La>80 nm; d002<0.3358 nm, and the degree of graphitization is 95% to 100%. The highly thermally conductive heat storage material comprises a carbonaceous part with a specific structure and a graphitic part with a specific structure, and the heat storage material obtained thereby possesses high thermal conductivity and high compressive strength.

Abstract: Provided are a display panel, a preparation method thereof, and a display device. The display panel includes a display substrate and a touch panel. The touch panel includes multiple touch electrodes. At least one of the touch electrodes includes multiple grid patterns enclosed by metal wires. At least one of the grid patterns includes a first edge, second edge, third edge and fourth edge that form a ring. The first edge and the third edge extend in a second direction. The second edge and the fourth edge extend in a first direction. A shape of the grid pattern includes a first curved ring, a second curved ring, a third curved ring, or a fourth curved ring. A first edge and third edge of the first curved ring are curves curved towards a direction opposite to the first direction.

Abstract: A composition for inhibiting intestinal permeability, treating leaky gut related diseases and/or preventing leaky gut related diseases including a Chinese herbal compound material or a Chinese herbal compound extract is provided. The Chinese herbal compound material includes Ganoderma, red jujube, longan and lotus seed. Moreover, the Chinese herbal compound extract includes a Ganoderma extract, a red jujube extract, a longan extract and a lotus seed extract.

Abstract: A display panel includes: a display substrate, a first barrier wall surrounding a display area, a blocking portion between the first barrier wall and the display area, a first encapsulation layer covering at least the display area, and touch wires. The blocking portion at least partially surrounds the display area. The first encapsulation layer includes a first surface, a second surface and a transition surface connecting the surfaces. On the display substrate, orthographic projections of the touch wires at least partially overlap with an orthographic projection on of the second surface, and are staggered with an orthographic projection of the transition surface; and at least a portion of the orthographic projection of the transition surface is located in a region between a border, away from the display area, of an orthographic projection of the blocking portion and an orthographic projection of a touch wire farthest away from the display area.

Abstract: A display panel, including an active area and a peripheral area, which is located outside of the active area, wherein the active area comprises a base substrate, and a display structure layer and a touch structure layer sequentially arranged on the base substrate; the peripheral area includes an isolation dam, a first ground trace and a second ground trace arranged on the base substrate; and the first ground trace is located at a side of the isolation dam close to the active area, and the second ground trace is located at a side of the isolation dam away from the active area.

Abstract: An integrated circuit structure includes a substrate, semiconductor devices, an inter-layer dielectric (ILD) structure, an interconnect, a dielectric layer, an etching barrier layer, a conductive layer, and memory units. The semiconductor devices are on the substrate. The ILD structure is over the semiconductor devices. The interconnect is in the ILD structure and electrically connected to the semiconductor devices. The dielectric layer is over the ILD structure. The etching barrier layer is on the first dielectric layer. The conductive layer is on the etching barrier layer. The memory units are stacked in a vertical direction over the etching barrier layer.

Abstract: An air valve structure arranged on a base comprises an air plug and a state-switching component. The air plug is arranged in an air chamber in an axial direction. The air plug includes a closing state to close the air hole, and an opening state to open the air hole. The state-switching component comprises a driving member that links the air plug, a shape-memory alloy (SMA) wire connected with the driving member, and at least one conductive member connected with the SMA wire. The driving member exerts an acting force to the air plug based on a condition of electricity provided by the conductive member for the SMA wire. The direction of the acting force is non-parallel with the axial direction and the air plug is moved and changed between the closing state and the opening state by the acting force.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

Abstract: A submicron-sized Pickering miniemulsion system stabilized by carbon quantum dots solid nanoparticles for biphasic catalysis is disclosed, which breaks the existing limits for homogenization of the immiscible biphasic system and overcomes the issues for big size of solid particles-stabilized emulsion droplets. A method for producing the carbon quantum dot-based catalysts and a process of establishing the Pickering miniemulsion system for biphasic reaction with enhanced catalytic efficiency are also disclosed. The carbon quantum dot-stabilized Pickering miniemulsion features a pH-responsive behavior, with a reversible transition between the emulsification and demulsification, triggering the easy & facile product separation and emulsifier/catalyst recycling in one reaction vessel.

Abstract: A device includes a substrate; semiconductor fins extending from the substrate; a liner layer on sidewalls of the semiconductor fins; an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins; an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials; a gate dielectric layer over a top surface of the isolation structure; and a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.