Patents by Inventor Chang-Won Park

Chang-Won Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8192842
    Abstract: Disclosed is a process for preparing polyurethane particulate and polyurethane particulate prepared therefrom. The polyurethane particulate has properties such that it is easy to control to a spherical form, the polyurethane particulate can be prepared in a desired particle size, the color thereof is stably exhibited, a washing process thereof is easy because almost no foam is generated in the washing process, and the preparation cost can be lowered because the particles do not lump and a separate grinding process is not needed, by using an inorganic suspension stabilizer in the manufacture process of the polyurethane particulate.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 5, 2012
    Assignee: Kolon Industries, Inc.
    Inventors: Chang Won Park, Young Seo Yoon
  • Publication number: 20110244329
    Abstract: Provided are a cathode active material for a lithium secondary battery and a lithium secondary battery including the same. The cathode active material includes a lithium composite oxide represented by the following Chemical Formula 1. Li[LizA]O2 A={M11-x-y(M10.78Mn0.22)x}M2y??[Chemical Formula 1] In Chemical Formula, M1 and M2 are independently one or more selected from a transition element, a rare earth element, or a combination thereof, M1 and M2 are elements that are different from each other, ?0.05?z?0.1, 0.8?x+y?1.8, and 0.05?y?0.35, and Ni has an oxidation number of 2.01 to 2.4.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 6, 2011
    Applicant: L F Material Co., Ltd.
    Inventors: Yoon Han Chang, Sang-Hoon Jeon, Chang-Won Park
  • Patent number: 8008784
    Abstract: A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a plurality of second notch-side pads. The first notch-side leads extend to a first side of the notch. The first notch-side pads are correspondingly disposed on the first notch-side leads. The second notch-side leads extend to a second side of the notch. The second notch-side pads are correspondingly disposed on the second notch-side leads. The sealant seals up the chip and the lead frame and exposes a lower surface of the lead frame. The notch exposes a portion of the sealant.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: August 30, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Young-Moon Hong, Chang-Suk Han, Chang-Won Park
  • Publication number: 20110042610
    Abstract: Disclosed is a method for preparing a cathode active material for a lithium secondary battery, and the preparing method includes: adding a phosphorus compound to a transition metal oxide dispersion liquid to prepare a coating liquid; drying the coating liquid to prepare a powder including phosphorus oxide coated on the surface of the transition metal oxide; and dry-mixing the powder coated with the phosphorus oxide with a lithium intercalation compound, and then firing the mixture to form a solid solution compound of Li-M1-M2-P—O (where M1 is a transition metal derived from transition metal oxide, and M2 is a metal derived from lithium intercalation compound) on the surface of the lithium intercalation compound. The method for preparing a cathode active material for a lithium secondary battery simplifies the conventional preparing process to save process cost, and it provides comparable electrochemical characteristics to a cathode active material obtained from a wet process.
    Type: Application
    Filed: March 24, 2009
    Publication date: February 24, 2011
    Applicant: L & F CO. LTD.
    Inventors: Jaephil Cho, Junho Eom, Yoon Han Chang, Chang-Won Park, Seung-Won Lee, Sang-Hoon Jeon, Byung Do Park
  • Patent number: 7895499
    Abstract: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: February 22, 2011
    Assignee: Korea Electronics Technology Institute
    Inventors: Ki-Man Jeon, Chang-Won Park, Young-Hwan Kim, Ki-Tae Kim, Hyun-bean Yi, Sung-Ju Park
  • Patent number: 7840348
    Abstract: An output control method of voice guidance signal in navigation system, the method comprising: searching for a travel route from a starting location to a destination of a vehicle; guiding the vehicle to travel along the searched travel route, and determining a current vehicle location if the vehicle is traveling, searching for a target location to be guided ahead of the traveling vehicle; generating a voice guidance signal for the searched target location to be guided; determining the priorities of a plurality of voice guidance signals in advance and outputting the voice guidance signals in sequence according to the predetermined priorities if the plurality of voice guidance signals conflict thereamong.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: November 23, 2010
    Assignee: LG Electronics Inc.
    Inventors: Su Jin Kim, Chang Won Park, Hyun Woo Choi
  • Publication number: 20100084749
    Abstract: A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a plurality of second notch-side pads. The first notch-side leads extend to a first side of the notch. The first notch-side pads are correspondingly disposed on the first notch-side leads. The second notch-side leads extend to a second side of the notch. The second notch-side pads are correspondingly disposed on the second notch-side leads. The sealant seals up the chip and the lead frame and exposes a lower surface of the lead frame. The notch exposes a portion of the sealant.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 8, 2010
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Young-Moon Hong, Chang-Suk Han, Chang-Won Park
  • Publication number: 20100062254
    Abstract: Disclosed is a process for preparing polyurethane particulate and polyurethane particulate prepared therefrom. The polyurethane particulate has properties such that it is easy to control to a spherical form, the polyurethane particulate can be prepared in a desired particle size, the color thereof is stably exhibited, a washing process thereof is easy because almost no foam is generated in the washing process, and the preparation cost can be lowered because the particles do not lump and a separate grinding process is not needed, by using an inorganic suspension stabilizer in the manufacture process of the polyurethane particulate.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 11, 2010
    Applicant: KOLON INDUSTRIES., INC.
    Inventors: Chang Won Park, Young Seo Yoon
  • Patent number: 7673203
    Abstract: An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 2, 2010
    Assignee: Korea Electronics Technology Institute
    Inventors: Chang Won Park, Ki Man Jeon, Young Hwan Kim, Jae Gi Son, Hyun Bean Yi, Sung Ju Park
  • Patent number: 7440849
    Abstract: The present invention relates to a method for managing map data for a vehicle using a navigation system, wherein upon display of the map data, memory loading for the display of the map data can be quickly performed by reducing the number of access to a physical storage medium with an entire map stored therein. To this end, when a travel guide map is generated again based on a new location as the position of a vehicle varies, only a certain number of map segments are retrieved from a physical storage medium such as a CD-ROM to generate the travel guide map, thereby making map-displaying speed faster. Further, when the travel guide map is generated again based on the new location as the position of the vehicle varies, map data loading speed can be faster by preventing reusable map segments among map segments loaded on an operation memory from being unnecessarily deleted, retrieved again from the physical storage medium and inserted into the operation memory.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: October 21, 2008
    Assignee: LG Electronics Inc.
    Inventors: Chang Won Park, Young In Kim, Moon Jeung Joe
  • Publication number: 20080162767
    Abstract: Provided is a 4× framer/deframer module for PCI-Express and a framer/deframer device using the same. In the PCI-Express for high-rate data processing, delimiter and pad processing, and 4× framer shifting and arrangement/reverse arrangement for framing/deframing a frame format are performed to achieve a structure that facilitates reconfiguration and expansion, for example, a pipeline structure, so that the 4× framer/deframer module can operate without delay within a 250 MHz clock even when expansion to 32× is made.
    Type: Application
    Filed: October 29, 2007
    Publication date: July 3, 2008
    Applicant: Korea Electronics Technology Institute
    Inventors: Sang-Wook CHO, Jin-Kyu Kim, Sung-Ju Park, Hyun-Bean Yi, Chang-Won Park, Ki-Man Jeon
  • Patent number: 7296200
    Abstract: Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: November 13, 2007
    Assignee: Korea Electronics Technology Institute
    Inventors: Chang Won Park, Ki Man Jeon, Sung Ju Park, Kyeong Won Yeom, Tae Sik Kim
  • Publication number: 20070234177
    Abstract: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.
    Type: Application
    Filed: December 27, 2006
    Publication date: October 4, 2007
    Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Ki-Man Jeon, Chang-Won Park, Young-Hwan Kim, Ki-Tae Kim, Hyun-bean Yi, Sung-Ju Park
  • Patent number: 7266448
    Abstract: A navigation system of the present invention provides a user of a moving object with a return path on an original driving path when the moving object deviates from the original driving path. A method for searching the return path of the moving object for use in the navigation system comprises the steps of: searching and storing an original driving path of the moving object, and guiding the moving object along the searched driving path; deciding whether the moving object is deviated from the driving path; when the moving object is deviated from the driving path, deciding a start point and return points for returning the moving object on the original driving path; after searching respective paths from the start point to the return points, deciding a shortest path as an optimum return path; and guiding the moving object to the original driving path along the decided return path.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: September 4, 2007
    Assignee: LG Electronics Inc.
    Inventors: Chang Won Park, Moon Jeung Joe
  • Patent number: 7117413
    Abstract: A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control register controller controls a shift and update link configuration by activating the link control register. A switch switches the scan path between wrapped cores based on the link control configuration of the link control register. An output logic connects the link control register to a test data out (TDO) of the chip in case of testing on chip or cores of system on chip.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 3, 2006
    Assignee: Korea Electronics Technology Institute
    Inventors: Chang Won Park, Sung Ju Park, Hyung Su Lee, Jae Hoon Song
  • Publication number: 20040233075
    Abstract: An 8B/10B encoder/decoder including logic gates. The 8B/10B encoder including logic gates including a 5B/6B encoding block to compute 6 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 5 bit input data; a 3B/4B encoding block to compute 4 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 3 bit input data; and a disparity computation block to create and output a disparity in response to outputs and clocks of the 5B/6B encoding block and the 3B/4B encoding block. Thus, an 8B/10B encoder/decoder including logic gates uses a two-group logic combination method with emphasis on speed rather than size. The minimum number of stages for data processing at logic gate level guarantees more stable and fast operation.
    Type: Application
    Filed: December 29, 2003
    Publication date: November 25, 2004
    Inventors: Chang Won Park, Sung Ju Park, Tae Sik Kim, Hyung Soo Lee, Ki Man Cheon
  • Patent number: 6815887
    Abstract: An organic electroluminescent display (EL) device including a transparent substrate, a first electrode unit formed on the transparent substrate in a predetermined pattern and made of a transparent conductive material, an organic EL unit including organic layers having a predetermined pattern, stacked on the first electrode unit, a second electrode unit corresponding to the first electrode unit, formed on the organic EL unit in a predetermined pattern, and an encapsulation layer to encapsulate the first electrode unit, the organic EL unit and the second electrode unit to protect the same, the encapsulation layer including a first component and a second component made of one or more metals selected from the group consisting of iron (Fe), cobalt (Co), vanadium (V), titanium (Ti), aluminium (Al), silver (Ag) and platinum (Pt).
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Joon-bae Lee, Chang-won Park, Jin-woo Park, Dong-chan Shin
  • Publication number: 20040220729
    Abstract: A navigation system of the present invention provides a user of a moving object with a return path on an original driving path when the moving object deviates from the original driving path. A method for searching the return path of the moving object for use in the navigation system comprises the steps of: searching and storing an original driving path of the moving object, and guiding the moving object along the searched driving path; deciding whether the moving object is deviated from the driving path; when the moving object is deviated from the driving path, deciding a start point and return points for returning the moving object on the original driving path; after searching respective paths from the start point to the return points, deciding a shortest path as an optimum return path; and guiding the moving object to the original driving path along the decided return path.
    Type: Application
    Filed: December 31, 2003
    Publication date: November 4, 2004
    Inventors: Chang Won Park, Moon Jeung Joe
  • Patent number: 6674237
    Abstract: A plate for a plasma display panel includes a plate member formed of a transparent material, a series of electrodes formed in a predetermined pattern on the plate member, and a dielectric layer formed on the plate member to cover the electrodes, wherein the electrodes are formed of a dielectric first component, and a metallic second component of at least one metal selected from a group consisting of iron (Fe), cobalt (Co), vanadium (V), titanium (Ti), aluminum (Al), silver (Ag), silicon (Si), germanium (Ge), yttrium (Y), zinc (Zn), zirconium (Zr), tungsten (W), tantalum (Ta), copper (Cu), and platinum (Pt).
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: January 6, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Young-rag Do, Chang-won Park, Joon-bae Lee, Chaun-gi Choi
  • Patent number: 6627322
    Abstract: A functional film includes a transition layer having a first constituent and a second constituent having gradual content gradients according to a thickness of the functional film. The first constituent is at least one dielectric material selected from the group consisting of SiOx (x>1), MgF2, CaF2, Al2O3, SnO2, In2O3 and ITO, and the second constituent is at least one material selected from the group consisting of iron (Fe), cobalt (Co), titanium (Ti), vanadium (V), aluminum (Al), silver (Ag), silicon (Si), germanium (Ge), yttrium (Y), zinc (Zn), zirconium (Zr), tungsten (W) and tantalum (Ta).
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: September 30, 2003
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Chaun-gi Choi, Young-rag Do, Joon-bae Lee, Chang-won Park