Abstract: An apparatus for bonding substrates and a method of bonding substrates are provided. In accordance with one exemplary embodiment of the present invention, a first plate to mount a first substrate is provided. A chamber body movably connected to the first plate is provided. A second plate that is placed opposite to the first plate and a second substrate is mounted on the second plate is provided. A chamber lead having the second plate mounted inside is provided which is movably connected to the chamber body to move rotationally or linearly to open or close the chamber space with the chamber body. A pair of first alignment cameras is placed outside of the chamber space to scan the first substrate or the second substrate. A stage control unit is provided to move the first plate or the second plate to align the first substrate and the second substrate.

Abstract: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

Abstract: A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.

Abstract: Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a tunnel dielectric layer. A blocking dielectric layer is formed on the charge storing layer and a gate electrode layer is formed on the blocking dielectric layer.

Abstract: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer in which carriers induced by the fixed charge layer are accumulated is disposed below the fixed charge layer. The elements are segregated to a substrate of the semiconductor substrate from the inside of the semiconductor substrate by heat.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: A method for forming a p-channel metal-oxide semiconductor(PMOS) device is suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions. The method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: A method for forming a p-channel metal-oxide semiconductor(PMOS) device is suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions. The method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.

Abstract: A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.

Abstract: A method for forming a silicide layer of a semiconductor memory device is disclosed. A silicide layer is formed in an impurity junction region through a contact hole exposing the impurity junction region on a semiconductor substrate. Here, two thermal annealing processes are performed on the semiconductor substrate on which a metal layer is deposited, by using low and high temperature up speeds and maintaining the semiconductor substrate under the highest temperature for less than one second, and then dropping the temperature at high speed. The process for removing a portion of the metal layer which did not react is carried out. As a result, a shallow junction can be formed in a very small devices, and deterioration of an electrical property of the semiconductor device is minimized by reducing junction leakage current, which results in the rapid operation of the device.

Abstract: A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

Abstract: A method for forming a transistor of a semiconductor device, including the step of forming a channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.

Abstract: A method for forming a suicide layer of a semiconductor memory device is disclosed. A silicide layer is formed in an impurity junction region through a contact hole exposing the impurity junction region on a semiconductor substrate. Here, two thermal annealing processes are performed on the semiconductor substrate on which a metal layer is deposited, by using low and high temperature up speeds and maintaining the semiconductor substrate under the highest temperature for less than one second, and then dropping the temperature at high speed. The process for removing a portion of the metal layer which did not react is carried out. As a result, a shallow junction can be formed in a very small devices, and deterioration of an electrical property of the semiconductor device is minimized by reducing junction leakage current, which results in the rapid operation of the device.

Abstract: A method of selective epitaxial growth for a semiconductor device is disclosed. By employing a hydrogen gas as a selectivity promoting gas in addition to a chlorine gas conventionally used, the method can guarantee the selectivity of epitaxial growth and further increase the growth rate of an epitaxial layer. The method begins with loading a semiconductor substrate into a reaction chamber. The substrate has a mask layer, which is selectively formed thereon to define a first portion exposed beyond the mask layer and a second portion covered by the mask layer. Next, a source gas is supplied into the reaction chamber so that the source gas is adsorbed on the first portion and thus the epitaxial layer is selectively formed on the first portion. Then, the selectivity promoting gas including the H2 gas into the reaction chamber, whereby any nucleus of semiconductor material is removed from the mask layer.

Abstract: A method of selective epitaxial growth for a semiconductor device is disclosed. By employing a hydrogen gas as a selectivity promoting gas in addition to a chlorine gas conventionally used, the method can guarantee the selectivity of epitaxial growth and further increase the growth rate of an epitaxial layer. The method begins with loading a semiconductor substrate into a reaction chamber. The substrate has a mask layer, which is selectively formed thereon to define a first portion exposed beyond the mask layer and a second portion covered by the mask layer. Next, a source gas is supplied into the reaction chamber so that the source gas is adsorbed on the first portion and thus the epitaxial layer is selectively formed on the first portion. Then, the selectivity promoting gas including the H2 gas into the reaction chamber, whereby any nucleus of semiconductor material is removed from the mask layer.

Abstract: The present invention is directed to a method of manufacturing a semiconductor device having a triple-well structure, comprising the steps of: forming a first pattern of a semiconductor substrate having a first N-well forming area, a R-well forming area, a second N-well forming area and a P-well forming area; forming a first layer within the substrate at a predetermining depth by implanting a N-type impurity ion using the first pattern as a mask; forming a bottom N-well within the substrate at a predetermined depth by implanting a N-type impurity ion using the first pattern as a mask; removing the first pattern; forming a second pattern on the substrate; forming a first lateral N-well and a second lateral N-well by implanting a N-type impurity ion using the second pattern as a mask, and portions of the first and second lateral N-wells overlap with opposite edge portions of the bottom N-well, thereby forming a N-well; removing the second pattern; forming a third pattern on the substrate; forming a second defec