Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

Abstract: A control method of a touchpad is provided. The touchpad has a determination module including a neural network. The determination module is used to determine the type of object. When the user uses the touchpad, the touchpad uses the captured object feature data of the touch object to update the determination module. Therefore, when determining the type of the touch object, the updated determination module can more accurately determine the touch object used by the user, so as to improve the determination accuracy.

Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: Various embodiments of the teachings herein include an image processing system comprising: a video stream processing device configured to receive a video stream, segment the video stream into multiple frames of pictures arranged in chronological order, and distribute the multiple frames of pictures to edge computing devices in a connected edge computing device group; and a picture collecting device configured to receive pictures from the edge computing device group. The individual edge computing devices in the edge computing device group are each configured to subject the received pictures to target identification, and send the pictures marked with a region in which an identified target is located. The picture collecting device is further configured to restore in chronological order as a video stream the received pictures marked with target identification results.

Abstract: A light source assembly includes a first annular reflector, a second annular reflector and a plurality of first light source modules. The first annular reflector has a first reflective surface. The second annular reflector is coaxial with the first annular reflector. A radius of the first annular reflector is greater than that of the second annular reflector. The second annular reflector has a second reflective surface facing the first reflective surface. The first light source modules take a central axis of the first annular reflector as a center and annularly arranged around the center. The first light source modules provide first beams to the first reflective surface, which reflects the first beams to the second reflective surface. The second reflective surface reflects the first beams and makes the first beams emit along a direction parallel to a central axis of the second annular reflector. A projection device is also provided.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: An image sensor is provided. The image sensor includes a substrate having a first pixel region and a second pixel region. The image sensor also includes a resonator structure disposed over the substrate. The resonator structure includes a first metal layer over the first pixel region and the second pixel region. The resonator structure also includes a first insulating layer over the first metal layer and the first pixel region. The first insulating layer has a first thickness. The resonator structure further includes a second insulating layer over the first metal layer and the second pixel region. The second insulating layer has a second thickness that is greater than the first thickness. In addition, the resonator structure includes a second metal layer over the first insulating layer and the second insulating layer.

Abstract: A user interface for designing, configuring and/or editing a control flow representing a control strategy associated with a semiconductor manufacturing process, the user interface including: a library of control elements having at least a control element representing a task of simulation and each control element being selectable by a user; a control flow editor configured to organize the control elements into a control flow representing the control strategy; and a communication interface for communicating the control flow to a calculation engine configured to evaluate the control flow.

Abstract: A method for determining a correction to a patterning process. The method includes obtaining a plurality of qualities of the patterning process (e.g., a plurality of parameter maps, or one or more corrections) derived from metrology data and data of an apparatus used in the patterning process, selecting, by a hardware computer system, a representative quality from the plurality of qualities, and determining, by the hardware computer system, a correction to the patterning process based on the representative quality.

Abstract: A method for determining a correction to a patterning process. The method includes obtaining a plurality of qualities of the patterning process (e.g., a plurality of parameter maps, or one or more corrections) derived from metrology data and data of an apparatus used in the patterning process, selecting, by a hardware computer system, a representative quality from the plurality of qualities, and determining, by the hardware computer system, a correction to the patterning process based on the representative quality.

Abstract: A coating apparatus includes a process chamber, a rotation device, and a rotation holder. The rotation device is disposed in the process chamber. The rotation holder is connected to the rotation device. The rotation holder includes two extension elements, two retaining elements, and two pins. The two extension elements are disposed around a center axis and separated from each other, wherein each of the two extension elements has a side surface. Each of the two retaining elements has a bottom surface, one of the two retaining elements is connected to one of the side surfaces, and the other of the two retaining elements is connected to the other of the side surfaces. One of the two pins is connected to one of the bottom surfaces, and the other of the two pins is connected to the other of the bottom surfaces.

Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of first dielectric layers, a plurality of metal layers of Ag or its alloy and a plurality of second dielectric layers are formed over the substrate. The plurality of first dielectric layers and the plurality of metal layers are alternately formed over the substrate. The plurality of second dielectric layers are formed on one side away from the substrate of the plurality of metal layers and located between the plurality of metal layers and the plurality of first dielectric layers. An optical element fabricated by the method is also provided.

Abstract: A user interface for designing, configuring and/or editing a control flow representing a control strategy associated with a semiconductor manufacturing process, the user interface including: a library of control elements having at least a control element representing a task of simulation and each control element being selectable by a user; a control flow editor configured to organize the control elements into a control flow representing the control strategy; and a communication interface for communicating the control flow to a calculation engine configured to evaluate the control flow.

Abstract: A method for determining a correction to a patterning process. The method includes obtaining a plurality of qualities of the patterning process (e.g., a plurality of parameter maps, or one or more corrections) derived from metrology data and data of an apparatus used in the patterning process, selecting, by a hardware computer system, a representative quality from the plurality of qualities, and determining, by the hardware computer system, a correction to the patterning process based on the representative quality.

Abstract: A coating apparatus includes a process chamber, a rotation device, and a rotation holder. The rotation device is disposed in the process chamber. The rotation holder is connected to the rotation device. The rotation holder includes two extension elements, two retaining elements, and two pins. The two extension elements are disposed around a center axis and separated from each other, wherein each of the two extension elements has a side surface. Each of the two retaining elements has a bottom surface, one of the two retaining elements is connected to one of the side surfaces, and the other of the two retaining elements is connected to the other of the side surfaces. One of the two pins is connected to one of the bottom surfaces, and the other of the two pins is connected to the other of the bottom surfaces.

Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of first dielectric layers, a plurality of metal layers of Ag or its alloy and a plurality of second dielectric layers are formed over the substrate. The plurality of first dielectric layers and the plurality of metal layers are alternately formed over the substrate. The plurality of second dielectric layers are formed on one side away from the substrate of the plurality of metal layers and located between the plurality of metal layers and the plurality of first dielectric layers. An optical element fabricated by the method is also provided.

Abstract: A wafer shipping box includes a case and a positioning unit. The case includes a base, a cover, and a receiving space defined by the base and the cover. The positioning unit is disposed in the receiving space and includes a lower retaining member connected to the base, an upper retaining member connected to the cover, and a cassette disposed therebetween. The cassette includes two upright holding walls spaced apart from each other, each of which has a plurality of lateral confining slots aligned in a front-rear direction. The lower retaining member is formed with a plurality of lower confining slots, each of which is defined by two slot walls interconnected at bottom ends thereof to form a slot bottom. The slot bottoms are respectively misaligned from central positions of the lateral confining slots along the front-rear direction.