Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

Abstract: A semiconductor device includes a substrate, a P-well region, a first N-type metal oxide semiconductor (NMOS) transistor provided in the P-well region, a second NMOS transistor provided on the substrate, and a common body bias region provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.

Abstract: A semiconductor device includes word lines disposed on a substrate and spaced apart in a first direction perpendicular to an upper surface of the substrate, a string select line disposed on the word lines, memory strings extending in the first direction on the substrate, each memory string including a first channel extending in the first direction through the word lines, and memory cells constituted by the word lines around the first channel, bit lines electrically connected to the memory strings, and a strapping line connected to the string select.

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.

Abstract: A programming method includes a first program loop applying first and second pulses to a selected word line and thereafter determining a threshold voltage for the selected memory cell in relation to first and second verification voltages. Then, upon determining that the threshold voltage is lower than the first verification voltage, performing the second program loop by applying the first pulse to the selected word line, or upon determining that the threshold voltage is higher than the first verification voltage and lower than the second verification voltage, performing the second program loop by applying the second pulse to the selected word line.

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract: A programming method includes a first program loop applying first and second pulses to a selected word line and thereafter determining a threshold voltage for the selected memory cell in relation to first and second verification voltages. Then, upon determining that the threshold voltage is lower than the first verification voltage, performing the second program loop by applying the first pulse to the selected word line, or upon determining that the threshold voltage is higher than the first verification voltage and lower than the second verification voltage, performing the second program loop by applying the second pulse to the selected word line.