Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

Abstract: Method for performing an erase program operation. Various methods include: erasing a block of cells by: applying a program pulse to a block of memory elements in the three-dimensional memory that programs the block of memory elements to a level below an erase verify level, where the three-dimensional memory comprises memory elements stacked vertically; performing a verify step to verify voltage levels of a group of memory elements; determining that a memory element of the group is outside of a threshold window defined between the erase verify level and a compact erase threshold amount; and applying a second program pulse to the memory element. Where erasing the block of memory elements creates an erased block, where a width of the voltage distribution of the erased memory elements in the erased block is the same as or below a width of a voltage distribution associated with programmed memory elements.

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn?1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn?1<VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn?1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn?1<VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn?1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.

Abstract: Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

Abstract: Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.