Patents by Inventor Channing P. Favreau

Channing P. Favreau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Orthogonal printed circuit board interface
    Patent number: 11990677
    Abstract: A dual-polarized PCB array antenna includes one or more PCBs and a radiating antenna array. Each PCB has a PCB mounting surface that extends from a first PCB end to an opposing second PCB end. The radiating antenna array includes one or more radiator substrates. Each radiator substrate has a patch mounting surface that extends from a first substrate end to an opposing second substrate end. The dual-polarized PCB array antenna further includes one or more orthogonal interfaces configured to arrange the patch mounting surface of a given radiator substrates in an orthogonal position with respect to the PCB mounting surface of a given PCB.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 21, 2024
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, Channing P. Favreau, Erika Klek
  • Electromechanical assembly having integrated conductor
    Patent number: 11949216
    Abstract: Methods and apparatus for a housing assembly including a housing comprising a conductive material, a conductor extending through the housing, and a dielectric material at least partially surrounding the conductor. Portions of the housing may surround the conductor such that the conductor, the dielectric, and the portions of the housing form a channel through the housing.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: April 2, 2024
    Assignee: Raytheon Company
    Inventors: Channing P. Favreau, Alexander Gilbert, Thomas V. Sikina
  • ELECTROMECHANICAL ASSEMBLY HAVING INTEGRATED CONDUCTOR
    Publication number: 20230231371
    Abstract: Methods and apparatus for a housing assembly including a housing comprising a conductive material, a conductor extending through the housing, and a dielectric material at least partially surrounding the conductor. Portions of the housing may surround the conductor such that the conductor, the dielectric, and the portions of the housing form a channel through the housing.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 20, 2023
    Applicant: Raytheon Company
    Inventors: Channing P. Favreau, Alexander Gilbert, Thomas V. Sikina
  • ORTHOGONAL PRINTED CIRCUIT BOARD INTERFACE
    Publication number: 20220294123
    Abstract: A dual-polarized PCB array antenna includes one or more PCBs and a radiating antenna array. Each PCB has a PCB mounting surface that extends from a first PCB end to an opposing second PCB end. The radiating antenna array includes one or more radiator substrates. Each radiator substrate has a patch mounting surface that extends from a first substrate end to an opposing second substrate end. The dual-polarized PCB array antenna further includes one or more orthogonal interfaces configured to arrange the patch mounting surface of a given radiator substrates in an orthogonal position with respect to the PCB mounting surface of a given PCB.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Thomas V. Sikina, Channing P. Favreau, Erika Klek
  • Reactive array
    Patent number: 11336032
    Abstract: Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, Channing P. Favreau
  • PCB cavity mode suppression
    Patent number: 11317502
    Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, William J. Clark, Channing P. Favreau, Erika Klek, Mikhail Pevzner, Donald G. Hersey, Gregory G. Beninati, Thomas J. Tellinghuisen
  • REACTIVE ARRAY
    Publication number: 20210359429
    Abstract: Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, Channing P. Favreau
  • PCB CAVITY MODE SUPPRESSION
    Publication number: 20210360772
    Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, William J. Clark, Channing P. Favreau, Erika Klek, Mikhail Pevzner, Donald G. Hersey, Gregory G. Beninati, Thomas J. Tellinghuisen