Patents by Inventor Chanrae Cho

Chanrae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of treating a single crystal silicon ingot to improve the LLS ring/core pattern
    Patent number: 11124893
    Abstract: A method is disclosed for reducing the size and density of defects in a single crystal silicon wafer. The method involves subjected a single crystal silicon ingot to an anneal prior to wafer slicing.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 21, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: WonJin Choi, JunHwan Ji, UiSung Jung, JungHan Kim, YoungJung Lee, ChanRae Cho
  • METHOD OF TREATING A SINGLE CRYSTAL SILICON INGOT TO IMPROVE THE LLS RING/CORE PATTERN
    Publication number: 20190194821
    Abstract: A method is disclosed for reducing the size and density of defects in a single crystal silicon wafer. The method involves subjected a single crystal silicon ingot to an anneal prior to wafer slicing.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 27, 2019
    Inventors: WonJin Choi, JunHwan Ji, UiSung Jung, JungHan Kim, YoungJung Lee, ChanRae Cho
  • EPITAXIAL WAFER HAVING A HEAVILY DOPED SUBSTRATE AND PROCESS FOR THE PREPARATION THEREOF
    Publication number: 20110250739
    Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • SUPPRESSION OF OXYGEN PRECIPITATION IN HEAVILY DOPED SINGLE CRYSTAL SILICON SUBSTRATES
    Publication number: 20110177682
    Abstract: This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
    Type: Application
    Filed: February 4, 2011
    Publication date: July 21, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • EPITAXIAL WAFER HAVING A HEAVILY DOPED SUBSTRATE AND PROCESS FOR THE PREPARATION THEREOF
    Publication number: 20090252974
    Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
    Publication number: 20090004426
    Abstract: This invention generally relates to a process for suppressing oxygen precipitation in epitaxial silicon wafers having a heavily doped silicon substrate and a lightly N-doped silicon epitaxial layer by dissolving existing oxygen clusters and precipitates within the substrate. Furthermore, the formation of oxygen precipitates is prevented upon subsequent oxygen precipitation heat treatment.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
  • Diffusion Control in Heavily Doped Substrates
    Publication number: 20090004458
    Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani