Patents by Inventor Chany-Hyun Lee

Chany-Hyun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6881626
    Abstract: A non-volatile memory device includes a bitline area, a string selection transistor, a plurality of memory transistors, a ground selection transistor, and a source area which are serially disposed. The memory transistors are silicon-oxide-nitride-oxide-silicon (SONOS) transistors having a multi-layered charge storage layer. The memory transistors are also depletion mode transistors having a negative threshold voltage. In a method of fabricating the non-volatile memory device, a first conductive type diffusion layer is formed at a predetermined area of a first conductive type substrate. Impurities of a second conductive type are implanted into a predetermined area of a surface of the substrate where the first conductive type diffusion layer is formed, thereby forming an inversely doped area at a surface of the first conductive type diffusion layer. A string selection gate, a plurality of memory gates, and a ground selection gate are formed over a predetermined area of the first conductive type diffusion layer.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chany-Hyun Lee, Jung-Dal Choi
  • Publication number: 20040235233
    Abstract: A non-volatile memory device includes a bitline area, a string selection transistor, a plurality of memory transistors, a ground selection transistor, and a source area which are serially disposed. The memory transistors are silicon-oxide-nitride-oxide-silicon (SONOS) transistors having a multi-layered charge storage layer. The memory transistors are also depletion mode transistors having a negative threshold voltage. In a method of fabricating the non-volatile memory device, a first conductive type diffusion layer is formed at a predetermined area of a first conductive type substrate. Impurities of a second conductive type are implanted into a predetermined area of a surface of the substrate where the first conductive type diffusion layer is formed, thereby forming an inversely doped area at a surface of the first conductive type diffusion layer. A string selection gate, a plurality of memory gates, and a ground selection gate are formed over a predetermined area of the first conductive type diffusion layer.
    Type: Application
    Filed: June 10, 2004
    Publication date: November 25, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chany-Hyun Lee, Jung-Dal Choi
  • Patent number: 6774433
    Abstract: A non-volatile memory device includes a bitline area, a string selection transistor, a plurality of memory transistors, a ground selection transistor, and a source area which are serially disposed. The memory transistors are silicon-oxide-nitride-oxide-silicon (SONOS) transistors having a multi-layered charge storage layer. The memory transistors are also depletion mode transistors having a negative threshold voltage. In a method of fabricating the non-volatile memory device, a first conductive type diffusion layer is formed at a predetermined area of a first conductive type substrate. Impurities of a second conductive type are implanted into a predetermined area of a surface of the substrate where the first conductive type diffusion layer is formed, thereby forming an inversely doped area at a surface of the first conductive type diffusion layer. A string selection gate, a plurality of memory gates, and a ground selection gate are formed over a predetermined area of the first conductive type diffusion layer.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: August 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chany-Hyun Lee, Jung-Dal Choi
  • Publication number: 20030123307
    Abstract: A non-volatile memory device includes a bitline area, a string selection transistor, a plurality of memory transistors, a ground selection transistor, and a source area which are serially disposed. The memory transistors are silicon-oxide-nitride-oxide-silicon (SONOS) transistors having a multi-layered charge storage layer. The memory transistors are also depletion mode transistors having a negative threshold voltage. In a method of fabricating the non-volatile memory device, a first conductive type diffusion layer is formed at a predetermined area of a first conductive type substrate. Impurities of a second conductive type are implanted into a predetermined area of a surface of the substrate where the first conductive type diffusion layer is formed, thereby forming an inversely doped area at a surface of the first conductive type diffusion layer. A string selection gate, a plurality of memory gates, and a ground selection gate are formed over a predetermined area of the first conductive type diffusion layer.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 3, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chany-Hyun Lee, Jung-Dal Choi