Abstract: A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved.

Abstract: A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other and have a connecting area, wherein the second array cell is shifted a distance along the connecting area. Therefore, the result of yield enhancement is achieved.

Abstract: A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall doping process is performed to form a doped region in the substrate at the upper trench sidewall. The blocking layer is removed from the trench. Because the blocking layer prevent dopants from reaching the bottom half of the trench during the sidewall doping process, junction leakage at the bottom section of the trench is prevented.

Abstract: A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall doping process is performed to form a doped region in the substrate at the upper trench sidewall. The blocking layer is removed from the trench. Because the blocking layer prevent dopants from reaching the bottom half of the trench during the sidewall doping process, junction leakage at the bottom section of the trench is prevented.

Abstract: The present invention provides a method for forming a bottle-shaped trench in a semiconductor substrate. The method shields the circumferential wall of the section of a first depth of a trench with a collar, and expands the cross sectional area of the section of a second depth of the trench by using a wet etchant. A bottle-shaped trench in a semiconductor substrate is then formed.

Abstract: A method of etching in a plasma etching chamber having an upper electrode and a susceptor is disclosed. The method comprises: setting the upper electrode and the susceptor to a first predetermined distance; performing a first etch at the first predetermined distance for a first predetermined time; setting the upper electrode and the susceptor to a second predetermined distance; and performing a first etch at the second predetermined distance for a second predetermined time.

Abstract: A method for manufacturing a transistor device that includes forming an oxide layer over a substrate, forming a gate structure over the oxide layer, depositing a silicon nitride layer over the oxide layer and the gate structure, anisotropic etching the silicon nitride layer to remove portions of the silicon nitride layer, wherein remaining portions of the silicon nitride layer form nitride spacers contiguous with the gate structure, and a portion of the oxide layer beneath the removed portions of the silicon nitride layer is also removed, cleaning oxide layer, applying a diluted hydrogen fluoride solution to the oxide layer to form a substantially uniform thickness of the oxide layer, and implanting ions through the oxide layer having a substantially uniform thickness to form source and drain regions of the transistor device.

Abstract: A method of planarizing an isolation region. Key elements of the invention include the two chemical-mechanical polish (CMP) steps and the CMP stop structure comprised of a sacrificial oxide layer and the second nitride layer. First a pad oxide layer, a first nitride layer, a sacrificial oxide layer and a second nitride layer are formed over a substrate. A trench is formed through the pad oxide layer, the first nitride layer, the sacrificial oxide layer and the second nitride layer and in the substrate. An oxide layer is deposited filling the trench and over the second nitride layer. The oxide layer is preferably formed by a high density plasma chemical vapor deposition (HDPCVD) deposition. In a first CMP step, we chemical-mechanical polish the oxide layer and the second nitride layer down to a level. The second nitride layer and the sacrificial oxide layer are then removed.

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract: A high density semiconductor memory device is provided. The memory device includes a transistor and a capacitor formed along the sidewall of a trench. The trench is formed below the crossing of a word line and a bit line. The capacitor is formed by diffusing dopants into the substrate surrounding the lower portion of the trench, depositing an insulating layer, and depositing a conducting layer into the trench. The transistor is formed in the substrate adjacent to the upper sidewall of the trench. The source region is formed by thermal drive-in, and the drain region is formed by ion-implantation. The gate electrode is formed by depositing a conducting material into the trench. A gate contact window connects the gate electrode to the word line, and a drain contact window connects the drain to the bit line. The drain region of two adjacent memory cells are connected, and share the same drain contact window.

Abstract: A method and structure are achieved for making an array of high-density memory cells for DRAMs. The high density is achieved by forming vertical cylindrical transistors aligned over deep-trench capacitors in a silicon substrate. The method consists of forming a field oxide around and extending inward over a portion of polysilicon trench capacitor electrodes. A gate isolation oxide and an array of word lines are formed aligned over the trench capacitor electrodes, and openings are etched in the word lines to the trench capacitor electrodes. Source contacts are implanted in the trench capacitor electrodes exposed in the openings. A gate oxide for the vertical transistors (FETs) is formed on the sidewalls in the openings, and a P doped polysilicon is formed in the openings for the FET channels. The vertical transistors are then completed by forming a drain implant in the FET channels, and a polysilicon layer is deposited and patterned to form an array of bit lines.

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.