Abstract: The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.

Abstract: The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.

Abstract: An electro-thinning apparatus for removing excess metal from the surface metal layer of the substrate is provided. The apparatus includes an electrolysis bath, a transportation system, an anode roller, a cathode roller, and at least one shielding plate. The electrolysis bath contains an electrolysis liquid. The transportation system is disposed in the electrolysis bath for moving a substrate from an upstream end to a downstream end. The anode roller is disposed relative to the electrolysis bath and located upstream to the transportation system. The cathode roller is located above the transportation system and located downstream to the anode roller. The at least one shielding plate is located downstream to the cathode roller. During electrolysis, the anode roller contacts a surface metal layer of the substrate while the cathode roller is partly immersed in the electrolysis liquid and away from the surface metal layer of the substrate during electrolysis.

Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.

Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.

Abstract: An electro-thinning apparatus for removing excess metal from the surface metal layer of the substrate is provided. The apparatus includes an electrolysis bath, a transportation system, an anode roller, a cathode roller, and at least one shielding plate. The electrolysis bath contains an electrolysis liquid. The transportation system is disposed in the electrolysis bath for moving a substrate from an upstream end to a downstream end. The anode roller is disposed relative to the electrolysis bath and located upstream to the transportation system. The cathode roller is located above the transportation system and located downstream to the anode roller. The at least one shielding plate is located downstream to the cathode roller. During electrolysis, the anode roller contacts a surface metal layer of the substrate while the cathode roller is partly immersed in the electrolysis liquid and away from the surface metal layer of the substrate during electrolysis.

Abstract: A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.

Abstract: A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.

Abstract: A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying and conveying a substrate. The first pick-up device is for picking up one of the dies and placing each die on the arranging platform. The second pick-up device is for picking up the dies on the arranging platform and placing the dies on the substrate at the same time.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.

Abstract: A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying and conveying a substrate. The first pick-up device is for picking up one of the dies and placing each die on the arranging platform. The second pick-up device is for picking up the dies on the arranging platform and placing the dies on the substrate at the same time.

Abstract: A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on the first substrate. Next, the defected packaging unit is removed from the first substrate to correspondingly form at least one opening in the first substrate. Then, a second substrate including at least one second packaging unit is provided. Later, the second packaging unit is separated from the second substrate. The area of the second packaging unit is less than that of the opening. Subsequently, the second packaging unit is disposed in the opening. The edge of the second packaging unit is placed partially against an inner wall of the opening.

Abstract: A wire-bonding apparatus is used for wire-bonding at least a first chip and a second chip on a substrate at the same time. The wire-bonding apparatus includes at least a first capillary, a second capillary, a driving unit, a processing unit and a database. The driving unit is used for driving the first capillary and the second capillary. The processing unit is used for outputting a command to the driving unit to control the first capillary and the second capillary. The database is used for storing an operating parameter data. The processing unit controls the first capillary and the second capillary according to the operating parameter data.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A method of forming a plurality of bumps over a wafer mainly comprises providing the wafer having a plurality of bonding pads formed thereon, forming an under bump metallurgy (UBM) layer over the bonding pads wherein the UBM layer includes an adhesive layer, for example a titanium (Ti) layer or an aluminum (Al) layer, and at least one electrically conductive layer formed on the adhesive layer, removing the portions of the electrically conductive layer located outside the bonding pads, forming a plurality of bumps over the residual portions of the electrically conductive layer disposed above the bonding pads, etching the adhesive layer located outside the bumps, and then reflowing the bumps.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A bumping process mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming a patterned adhesive layer over the bonding pads, forming a barrier layer and a wetting layer on the patterned adhesive layer and the surface of the wafer, removing the barrier layer and the wetting layer not covering the patterned adhesive layer, forming a plurality of bumps on the patterned wetting layer and reflowing the bumps.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.