Patents by Inventor Chao-Hsien Huang
Chao-Hsien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220013411Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
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Patent number: 11205706Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.Type: GrantFiled: October 18, 2019Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Chao-Ching Cheng, Tzu-Chiang Chen, Chao-Hsien Huang
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Patent number: 11195759Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.Type: GrantFiled: October 1, 2019Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Wei-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin
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Publication number: 20210327764Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.Type: ApplicationFiled: June 29, 2021Publication date: October 21, 2021Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Patent number: 11056393Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.Type: GrantFiled: March 11, 2019Date of Patent: July 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Publication number: 20210202712Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Patent number: 10964795Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: GrantFiled: September 10, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Patent number: 10949164Abstract: A volume of sound adjustment method includes the following steps: outputting an audio with a played volume; detecting a volume of environmental noise; comparing the volume of environmental noise with a setting volume, and setting the lower one as a first target volume and setting the higher one as a second target volume; and gradually adjusting the played volume from the first target volume to the second target volume at an adjusting speed. In addition, an electronic device for adjusting a volume and a non-transitory computer readable storage medium device are also disclosed.Type: GrantFiled: February 18, 2020Date of Patent: March 16, 2021Assignee: ASUSTEK COMPUTER INC.Inventors: Yen-Ling Chen, Pu-Chien Lee, Jen-Pang Hsu, Chao-Hsien Huang, Chih-Hsien Yang
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Patent number: 10861953Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: GrantFiled: April 30, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Publication number: 20200287047Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
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Publication number: 20200272411Abstract: A volume of sound adjustment method includes the following steps: outputting an audio with a played volume; detecting a volume of environmental noise; comparing the volume of environmental noise with a setting volume, and setting the lower one as a first target volume and setting the higher one as a second target volume; and gradually adjusting the played volume from the first target volume to the second target volume at an adjusting speed. In addition, an electronic device for adjusting a volume and a non-transitory computer readable storage medium device are also disclosed.Type: ApplicationFiled: February 18, 2020Publication date: August 27, 2020Inventors: Yen-Ling CHEN, Pu-Chien LEE, Jen-Pang HSU, Chao-Hsien HUANG, Chih-Hsien YANG
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Patent number: 10755943Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.Type: GrantFiled: December 17, 2018Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching
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Patent number: 10680109Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.Type: GrantFiled: September 25, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
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Publication number: 20200176320Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.Type: ApplicationFiled: October 1, 2019Publication date: June 4, 2020Inventors: Wei-Lun CHEN, Chao-Hsien HUANG, Li-Te LIN, Pinyen LIN
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Patent number: 10636891Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.Type: GrantFiled: November 21, 2018Date of Patent: April 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Chao-Ching Cheng, Tzu-Chiang Chen, Chao-Hsien Huang
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Publication number: 20200105604Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.Type: ApplicationFiled: March 11, 2019Publication date: April 2, 2020Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Publication number: 20200052086Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Yu-Lin YANG, Tung Ying LEE, Shao-Ming YU, Chao-Ching CHENG, Tzu-Chiang CHEN, Chao-Hsien HUANG
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Publication number: 20200006515Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Publication number: 20190334008Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Patent number: 10361278Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.Type: GrantFiled: October 5, 2017Date of Patent: July 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Chao-Ching Cheng, Tzu-Chiang Chen, Chao-Hsien Huang