Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.

Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.

Abstract: A phase-lock loop (PLL) has an oscillator comprising a plurality of operating curves. A method for implementing a multi-transfer curve in a phase lock loop. A means of a finite state machine cooperating with a current cell, the unwanted loop gain is effectively reduced to produce a wide-ranging operating curve.

Abstract: A phase-lock loop (PLL) has an oscillator comprising a plurality of operating curves. A method for implementing a multi-transfer curve in a phase lock loop. By means of a finite state machine cooperating with a current cell, the unwanted loop gain is effectively reduced to produce a wide-ranging operating curve.