Abstract: An audio output method and a system including first and second electronic devices and an audio output device. The first and second devices are connected to a network using a system authentication account, the first device has installed thereon a music application, and the second device has installed thereon a voice call application. When the audio output device outputs an audio signal corresponding to audio data of the music application, in response to the second electronic receiving an incoming call from the voice call application, the first device displays a first prompt corresponding to the incoming call. The first device sends an indication of answering the incoming call to the second device, which answers the incoming call and sends audio data of the incoming call to the first device, and the first device causes the audio output device to output an audio signal corresponding to the audio data of the incoming call.

Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.

Abstract: A field programmable gate array (FPGA)-based parallel equalization method is provided. The method implements efficient equalization of communication data by means of a parallel pipeline filter structure and through a least mean square (LMS) algorithm capable of dynamically adjusting a step. Firstly, a tap coefficient of an equalization filter is calculated through the LMS algorithm capable of dynamically adjusting an iteration factor. Secondly, the efficiency of FPGA data processing is improved through a multistage pipeline and a multi-channel parallel data processing. According to the present disclosure, in each clock cycle, there are M channels of data inputted into the equalization filter in parallel, and at the same time, there are also M channels of data outputted in parallel, and thus the FPGA can efficiently perform equalization processing on data acquired by a high-speed analog-to-digital converter (ADC) through the parallel pipeline method.

Abstract: It is provided a high-linearity GaN HEMT radio frequency power device for improving a transconductance under a large signal, including a substrate layer, a buffer layer, a second barrier layer, a channel layer, a first barrier layer, and a protection layer arranged in sequence. A source, a gate, and a drain are arranged on the protection layer. A first two-dimensional electron gas and a second two-dimensional electron gas are respectively formed between the channel layer and the first barrier layer and between the channel layer and the second barrier layer. The source, the gate, and the drain are configured to receive an external control signal to control motion of electrons in the first two-dimensional electron gas and the second two-dimensional electron gas formed by the channel layer. In case of the large signal, electrons in the second two-dimensional electron gas flow into the first two-dimensional electron gas.

Abstract: A method for accelerating fast Fourier transform (FFT) based on field programmable gate array is provided. A sequence requiring N-point FFT is decomposed equally into 4 subsequences. The 4 subsequences are processed through 4 parallel FFT intellectual property (IP) cores. Finally, an arithmetic operation is performed on the processed data and twiddle factor data pre-stored in a memory to obtain a result of the N-point FFT of an original sequence. An FFT decomposition module, a twiddle factor storage module, and an operation processing module are provided. Through the processing method, a time delay consumed by an N-point FFT operation can be reduced, and excellent application value can be achieved in a high-speed digital signal processing system.

Abstract: This application provides an audio output method and a terminal device. The method helps to reduce the operation complexity of a user, improve a degree of intelligence of the terminal device, and finally improve the user experience. The method includes that: a second terminal device may send an audio output request to a first terminal device, and a user may operate the first terminal device or an audio output device connected to the first terminal device, to trigger the second terminal device to obtain audio data corresponding to the audio output request.

Abstract: A method is disclosed for a coprocessor of a device. The coprocessor may initiate, based on an instruction received from a processor, a wireless communication service required by the processor. The coprocessor further generates a drive instruction for driving a wireless communications module of the device to perform the wireless communication service, and then the coprocessor sends the drive instruction to the wireless communications module.

Abstract: The present disclosure provides a reconfigurable power amplifier (PA) based on a PIN switch and a design method thereof. The reconfigurable PA based on a PIN switch includes an input port, an input matching circuit, the PIN switch, a gate bias circuit, a transistor, a drain bias circuit, an output matching circuit and an output port, where the input matching network includes an input end connected to a power input end, and an output end connected to a gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain bias circuit is connected in parallel with a drain, the drain of the transistor is connected to an input end of the output matching circuit, and an output end of the output matching circuit serves as a power output.