Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.

Abstract: According to examples, a depth sensing apparatus may include an illumination source to output a light beam onto a polarizing beam separation element (PBSE). The PBSE may generate a right hand circularly polarized (RCP) beam and a left hand circularly polarized (LCP) beam to be projected onto a target area, in which the RCP beam and the LCP beam may create an interference with respect to each other. The depth sensing apparatus also includes an imaging component to capture an image of the target area with the RCP beam and the LCP beam projected on the target area, in which the captured image is to be analyzed for depth sensing of the target area. The depth sensing apparatus further includes a polarizer that may increase an intensity of the interference pattern.

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: Aspects of the technology described herein relate to built-in self-testing (BIST) of circuitry (e.g., a pulser or receive circuitry) and/or transducers in an ultrasound device. A BIST circuit may include a transconductance amplifier coupled between a pulser and receive circuitry, a capacitor network coupled between a pulser and receive circuitry, and/or a current source couplable to the input terminal of receive circuitry to which a transducer is also couplable. The collapse voltages of transducers may be characterized using BIST circuitry, and a bias voltage may be applied to the membranes of the transducers based at least in part on their collapse voltages. The capacitances of transducers may also be measured using BIST circuitry and a notification may be generated based on the sets of measurements.

Abstract: A method for spacer patterning includes performing a deposition process, the deposition process comprising conformally depositing an over layer over a spacer layer as deposited on top surfaces of a patterned mandrel layer and on sidewalls of the patterned mandrel layer, and performing an etch process using a fluorine containing etching gas. The etch process includes a post-deposition breakthrough process, removing portions of the over layer on the top surfaces of the patterned mandrel layer, and a main-etch process, removing shoulder portions of the over layer and shoulder portions of the spacer layer.

Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: A semiconductor element and a method for manufacturing the same are provided. The semiconductor element includes a plug and a via on the plug and electrically connected to the plug. The plug includes a tungsten plug and a conductive layer on the tungsten plug. The tungsten plug and the conductive layer include different materials. The tungsten plug has a first width in a lateral direction. The conductive layer has a second width in the lateral direction. The second width is greater than or equal to the first width. The conductive layer is between the via and the tungsten plug.

Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.

Abstract: A closed mode switch mechanism. The closed mode switch mechanism includes an antenna controller; an antenna coupled to the antenna controller; and, an antenna closed mode switch system coupled to the antenna controller and the antenna, the antenna closed mode switch system providing antenna impedance matching for the antenna when an information handling system is configured in a closed mode of operation.

Abstract: An ultrasonic imaging system includes an ultrasonic probe and a processing unit. The ultrasonic probe is operable at multiple different tilt angles to perform ultrasonic measurement and to obtain a plurality 2D ultrasonic images corresponding respectively to the different tilt angles. The processing unit calculates a 3D ultrasonic images based on the 2D ultrasonic images and the corresponding tilt angles.

Abstract: An antenna assembly for a portable information handling system. The antenna assembly includes an antenna bounding component, the antenna bounding component being electrically and physically connected to a top cover portion of the portable information handling system; and, an antenna, the antenna being mounted to the antenna bounding portion, radio frequency (RF) radiation radiating via an RF radiation path, the RF radiation path being provided by a radiation slot, the radiation slot being located within a bottom cover portion of the portable information handling system.

Abstract: A system and method for tracking actions of mobile assets used to perform a process within a facility includes a plurality of object trackers positioned throughout the facility to monitor, detect and digitize locations and actions, including movement, of a mobile asset within the facility. The mobile asset includes an identifier which is detectable by each object tracker to track the movement and location of the detected asset in real time. Each object tracker includes at least one sensor for monitoring and detecting the asset and its identifier, where the input sensed by the sensor is transmitted to a computer within the object tracker for time stamping with a detected time, and processing of the sensor input using one or more algorithms to identify the asset type associated with the detected identifier, and the asset's location in the facility at the detected time.