Patents by Inventor Chao-Lun Chiang

Chao-Lun Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 8068344
    Abstract: An electronic apparatus, which accommodates a chip card, includes a casing, a limit element and a carrier. The limit element is connected to the casing and has a protruding part. The carrier is slidingly disposed on the casing and has at least a contact area disposed on a side of the carrier. The limit element is located at a first position as the protruding part contacts the contact area, and the limit element is located at a second position as the protruding part is away from the contact area. The protruding part moves between the first position and the second position.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: November 29, 2011
    Assignee: Inventec Corporation
    Inventors: Chao-Lun Chiang, Chien-Chung Liao, Chih-Lin Ho
  • Publication number: 20100110646
    Abstract: An electronic apparatus, which accommodates a chip card, includes a casing, a limit element and a carrier. The limit element is connected to the casing and has a protruding part. The carrier is slidingly disposed on the casing and has at least a contact area disposed on a side of the carrier. The limit element is located at a first position as the protruding part contacts the contact area, and the limit element is located at a second position as the protruding part is away from the contact area. The protruding part moves between the first position and the second position.
    Type: Application
    Filed: November 4, 2009
    Publication date: May 6, 2010
    Inventors: Chao-Lun CHIANG, Chien-Chung LIAO, Chih-Lin HO