Abstract: In a method of connecting electric signals between electronic apparatus, various signal terminals or sockets used to connecting power supply, audio/video signals, or transmission cables are integrated into a stackable connection terminal interface. Each of the connection terminals provides a plurality of signal transmission paths or contacts, and is electrically connectable at two opposite ends thereof to enable sequential stacking of multiple connection terminals. The electric contacts on the stackable connection terminal are separately pre-assigned to a different signal transmission path, so that two or more stackable connection terminals in a stacked state may still own respective signal transmission path to ensure independent signal transmission without mutual interference. Therefore, the space occupied by different terminal interfaces is reduced, and a uniformly structured connection interface is provided.

Abstract: In a method of connecting electric signals between electronic apparatus, various signal terminals or sockets used to connecting power supply, audio/video signals, or transmission cables are integrated into a stackable connection terminal interface. Each of the connection terminals provides a plurality of signal transmission paths or contacts, and is electrically connectable at two opposite ends thereof to enable sequential stacking of multiple connection terminals. The electric contacts on the stackable connection terminal are separately pre-assigned to a different signal transmission path, so that two or more stackable connection terminals in a stacked state may still own respective signal transmission path to ensure independent signal transmission without mutual interference. Therefore, the space occupied by different terminal interfaces is reduced, and a uniformly structured connection interface is provided.

Abstract: An electric signal transmission connector assembly includes at least one plug and a receptacle mounted to an electronic apparatus. The plug and the receptacle are internally provided at two opposite positions with a permanent magnet each, so that the plug may be easily connected to the receptacle through magnetic attraction between the two magnets. The plug and the receptacle also include a plurality of terminals each. When the plug and the receptacle are magnetically connected to each other, the terminals thereof are contacted with one another to enable transmission of electric signals or supply of power via the plug and the receptacle. Two or more plugs may be stacked up to magnetically connect to the same one receptacle to save a lot of space by magnetically connecting a lower connecting section of an upper plug to an upper receiving section of a lower plug.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first magnification, followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A wireless input device charged through an attachable receiver includes a wireless input device operated by users for controlling a computer, and includes a receiver which is connected to the computer to receive the data from the input device and transmitting the data to the computer . The input device has a cavity and the cavity has a recharged plug inside for being recharged. When the battery of the wireless input device run out, the receiver has a recharged socket for transporting power through the recharged plug to the wireless input device.

Abstract: A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Abstract: A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric layer interposed. On the floating gate, a control gate is provided with a second dielectric layer interposed. The width of the floating gate is narrower than the active regions when viewed in transverse cross-section. A lighted doped region is optionally provided in the substrate at positions which are not covered by the floating gate. A manufacturing method for forming such memory device is also disclosed.

Abstract: A method is provided for forming a shallow trench isolation in a semiconductor structure is described as the followings: Firstly, a semiconductor substrate is provided, an oxide layer and a silicon layer are respectively formed. Subsequentially, an etching process is performed so that the semiconductor substrate owns a plurality of columns thereon. A second oxide layer is formed by the thermal oxidation. It is noticed that the original oxide layer is combined with the following second oxide layer as the second oxide layer. Consequentially increasing a thickness of the second oxide layer. Finally, the top surface of the third oxide layer is planazed until the silicon layer is exposed so that reducing damage in the semiconductor structure.

Abstract: A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric layer interposed. On the floating gate, a control gate is provided with a second dielectric layer interposed. The width of the floating gate is narrower than the active regions when viewed in transverse cross-section. A lighted doped region is optionally provided in the substrate at positions which are not covered by the floating gate. A manufacturing method for forming such memory device is also disclosed.

Abstract: A method for manufacturing a photomask of cylindrical capacitor arrays surrounded by a corrugated protection trench is provided. First, a capacitor array layout is generated, next, the capacitor array patterns are copied to protection trench area with exact the same shape and pitch, finally, the protection trench is finished by filling connecting patterns between gaps of the capacitor arrays. A corrugated close loop protection trench pattern can hence be developed upon photoresist through the exposing and is developing of a photo stepper.

Abstract: A method of making a nonvolatile memory device having a high capacitive coupling ratio with a self-aligned floating gate is disclosed. A tunnel dielectric layer, a first conductive layer, and a sacrificial layer are sequentially formed over a semiconductor substrate. Isolation trenches are etched in the substrate through the layers and filled with isolation oxides that protrude over the substrate. Subsequently, the sacrificial layer is removed to leave a cavity between the isolation oxides. A second conductive layer is conformally deposited over substrate, and then planarized or etched back to the isolation oxides. Next, the isolation oxides are etched back to expose additional surface of the second conductive layer. Finally, an inter-gate dielectric layer and a control gate layer are sequentially formed over the substrate.

Abstract: The present invention provides a storage node for a semiconductor device, and particularly for a DRAM cell in which a simplified and improved process is provided when compared to the conventional methods. The process involves the deposition of a single oxide layer which has a thickness substantially the same as the height of the storage node to be built, and then sequentially forming a node contact window and a node tub window in the oxide layer followed by a single deposition of a polysilicon material to form the node contact and the crown-shaped storage node simultaneously.

Abstract: A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region, self-aligned to the narrower, underlying polysilicon layer. Subsequent metallization results in metal coverage, only on the surfaces of the wider polysilicon layer. An anneal cycle then converts only the wider polysilicon feature to a metal silicide, resulting in a polycide gate structure, comprised of a wider, overhanging metal silicide layer, on a narrower, underlying polysiliocn layer.

Abstract: A process for forming a cylindrical shaped, storage node structure, for a DRAM capacitor, has been developed. The process features forming a capacitor opening, in an insulator layer, exposing the fop surface of a storage node plug structure, located at the periphery of the capacitor opening. The deposition of a conductive layer, followed by a blanket, anisotropic RIE procedure, results in the creation of a cylindrical shaped, storage node structure, on the sides of the capacitor opening, with contact to the underlying storage node plug structure, accomplished via a segment of the cylindrical shaped, storage node structure, overlying a portion of the top surface of the underlying storage node plug structure.