Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace.

Abstract: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device. The at least one first metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.

Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.

Abstract: A system includes a central processing unit (CPU); a memory device in communication with the CPU, and a direct memory access (DMA) controller in communication with the CPU and the memory device. The memory device includes a plurality of vertically stacked chips and a plurality of input/output (I/O) ports. Each of the I/O ports connected to at least one of the plurality of chips through a through silicon via. The DMA controller is configured to manage to transfer of data to and from the memory device.

Abstract: A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace.

Abstract: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.

Abstract: A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.

Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated.

Abstract: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.

Abstract: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device The at least one fist metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.

Abstract: An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.