Abstract: The present disclosure discloses a pixel circuit and a display panel. The pixel circuit includes a light emitting module and a driving module including at least two driving units connected in parallel. a quantity of displayable gray scales can be improved or increased by configuring at least two driving units connected in parallel in the driving module where the at least two driving units can each correspondingly configure a light emitting current so that a plurality of light emitting brightness of the light emitting module can be implemented by a sum of these light emitting currents.

Abstract: A method and apparatus comprising computer code configured to cause a processor or processors to determine more than one vertices in an input mesh, and group the more than one vertices in more than one group of vertices. The grouping of a respective vertex in a respective group may be based on a topological distance of the respective vertex. In embodiments, the processor or processors may also determine a set of filter coefficients for the more than one group of vertices; and signal the more than one group of vertices and the set of filter coefficients.

Abstract: A method and apparatus comprising computer code configured to cause a processor or processors to obtain a coded bitstream comprising a mesh sequence of a plurality of meshes of the 3D visual content and a displacement of a local coordinate system (LCS) or a global coordinate system (GCS) of at least one mesh of the plurality of meshes, the LCS or GCS being at a vertex of the at least one mesh, determine a projection coefficient of the displacement of the LCS or GCS, the projection coefficient indicating a unit tangent vector of the LCS or GCS in a normal direction to the vertex and is based on normalizing a tangent basis vector of the LCS or GCS, and decode the mesh sequence based on the projection coefficient of the displacement.

Abstract: In some examples, an apparatus for mesh processing includes processing circuitry. The processing circuitry receives a first mesh frame with polygons representing a surface of an object, and determining that the first mesh frame is a non manifold type mesh in response to one or more singularity components in the first mesh frame. The processing circuitry converts the first mesh frame to a second mesh frame that is a manifold type mesh. The first mesh frame has first boundary loops that respectively correspond to second boundary loops in the second mesh frame. The processing circuitry detects the second boundary loops in the second mesh frame, and determines the first boundary loops in the first mesh frame according to the second boundary loops in the second mesh frame.

Abstract: Disclosed is a driving circuit, a display panel and a display device. The driving circuit includes a plurality of cascaded driving units, where a first staged driving unit includes a forward and backward scan control module, a node signal control module, an output control module, a first voltage stabilizing module, a first pull-down module, a second pull-down module and an electrical leakage control module. The electrical leakage control module is configured to maintain a voltage level of an output signal of the forward and backward scan control module.

Abstract: A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a data writing module, a data conversion module, and a current driving module. The data writing module is electrically connected to a first node and configured to transmit a data signal to the first node. The data conversion module is electrically connected to the first node, a second node, and a modulation signal source, and configured to generate a current driving control signal, and to output the current driving control signal to the second node. The current driving module is electrically connected to the second node, a light-emitting control wire, and a light-emitting device, and configured to control the light-emitting device to emit light. An effective pulse of the current driving control signal has different pulse widths in different gray-scale states.

Abstract: In a method, a base mesh is generated from a down-sampled input mesh in a current frame, where the base mesh includes a plurality of vertices. A prediction mode to be applied to the base mesh is determined. The prediction mode is an inter prediction mode or an intra prediction mode. Based on the prediction mode being determined as the intra prediction mode, duplicate vertices among the plurality of vertices in the base mesh are merged to generate a subset of the plurality of vertices. At least the subset of the plurality of vertices is encoded based on the determined intra prediction mode to generate prediction information of at least the subset of the plurality of vertices.

Abstract: Method, apparatus, and system for texture coordinate prediction for mesh compression are provided. The process may include receiving, for a mesh, a coordinate of a first vertex and a coordinate of a prediction candidate vertex in a three dimensional (3D) space. The process may include determining a stretch perpendicular distance associated with the first vertex and the prediction candidate vertex, the stretch perpendicular distance being based on a conversion of the 3D space into a two dimensional (2D) space, and determining a 2D texture coordinate of the first vertex based on the stretch perpendicular distance associated with the first vertex and the prediction candidate vertex. The process may also include determining a residual of a predicted coordinate of the first vertex and an actual 2D coordinate of the first vertex; and compressing the mesh based on entropy coding the residual.

Abstract: For the problem of difficult roof anchor withdrawal at the end of a working face, a static crushing directional anchor withdrawal method at the end of a large-mining-height working face is provided. The method includes the following steps: designing key parameters of boreholes for static crushing, including a borehole position, a spacing between boreholes, a borehole depth, and a borehole diameter at the end of a working face; then determining parameters of a static crushing agent grouting technology device for the construction of a static crushing process; and carrying out an anchor withdrawal operation at the end.

Abstract: Aspects of the disclosure provide methods and apparatuses for mesh coding (e.g., compression and decompression). In some examples, an apparatus for mesh coding includes processing circuitry. The processing circuitry decodes a plurality of initial maps in two-dimension from a bitstream carrying a three-dimensional (3D) mesh frame. The processing circuitry determines at least two sampling rates associated with different portions of the plurality of initial maps and recovers from the plurality of initial maps and based on the at least two sampling rates associated with the different portions of the plurality of initial maps to obtain a plurality of recovered maps. A first portion of the plurality of initial maps is recovered based on a first sampling rate, and a second portion of the plurality of initial maps is recovered based on a second sampling rate. The processing circuitry reconstructs the 3D mesh frame based on the plurality of recovered maps.

Abstract: A processing circuitry decodes a plurality of maps in 2D from a bitstream carrying a mesh frame. The mesh frame represents a surface of an object with polygons. The plurality of maps includes a decoded geometry map and a decoded attribute map with an adaptive 2D atlas sampling applied. The processing circuitry determines at least a first sampling rate and a second sampling rate according to syntaxes signaled in the bitstream. The first sampling rate is applied to a first region of the mesh frame and the second sampling rate is applied to a second region of the mesh frame during the adaptive 2D atlas sampling. The processing circuitry reconstructs, based on the plurality of maps, at least a first vertex of the mesh frame according to the first sampling rate, and a second vertex of the mesh frame according to the second sampling rate.

Abstract: Coding information of a mesh is received. The coding information includes a plurality of first coordinates and a plurality of second coordinates corresponding to a plurality of vertices and a texture map that are associated with the mesh. A respective first coordinate and a respective second coordinate associated with each of the plurality of vertices are normalized by adjusting the respective first coordinate based on a first factor and the respective second coordinate based on a second factor. The first factor and the second factor are associated with at least one of (i) a bit depth value indicating a coded range of the first coordinates and the second coordinates and (ii) a size of the texture map. The normalized respective first coordinate and the normalized respective second coordinate are expanded based on the first factor and the second factor respectively.

Abstract: A thin film transistor and a display panel are provided. A first dimension of a first transmission portion electrically connected to a source heavily-doped portion is different from a second dimension of a second transmission portion electrically connected to a drain heavily-doped portion, so that an intensity of an electric field of carriers transmitted by the transmission portion corresponding to the larger one of the first dimension or the second dimension is smaller when the thin film transistor is turned on, thereby reducing the bombardment effect of the carriers on a source or a drain and improving the stability of thin film transistor.

Abstract: The present application provides a display panel and a display device. An N-th auxiliary unit is arranged in a display area of the display panel. An output end of the N-th auxiliary unit is connected to an N-th scan line. By connecting the auxiliary unit arranged in the display area to the corresponding scan line, a falling edge of a scan signal transmitted in the scan line can have sharp falling or a rising edge of the scan signal can have sharp rising, which can alleviate a signal distortion problem caused by transmission delay in the display area.

Abstract: A gate drive circuit and a display panel are provided. A pull-up module and a pull-down module of the gate drive circuit output a constant-voltage high potential to a second node, a third node, and a n-th stage gate drive signal through a P-type thin film transistor and output constant-voltage low potential through a N-type thin film transistor to the second node, the third node, and an n-th gate drive signal, thereby improving the stability of the output signal of the thin film transistor connected to the gate drive circuit and the key node.

Abstract: The present application discloses a gate drive circuit and a display device. The gate drive circuit includes a plurality of cascaded gate drive units, in which one of the gate drive units includes a first layout, an input module and a pull-up module. By receiving a potential changeable signal by the gate of a first transistor or the gate of a second thin-film transistor, it can alleviate or avoid current leakage caused when a first node keeps at a same voltage level for a long time, thereby improving the stability of the potential of the first node.

Abstract: An chip for integrated tumor cell behavior experiments, which comprises a functional area I, a functional area II, a functional area III, a functional area IV and a functional area V, wherein the functional area I comprises a cell invasion 3D co-culture plate (400) for cell invasion experiments; the functional area II comprises a cell migration culture hole (500) for cell migration experiments; the functional area III comprises a cell proliferation single-cell culture hole (600) for tumor single-cell culture; the functional area IV comprises an angiogenesis 3D co-culture plate (700) for tumor-related angiogenesis experiments; and the functional area V comprises a tumor single-cell culture hole (803), a matrix glue groove (805) and a tumor cell attraction factor hole (801) connected by matrix glue for tumor single-cell migration or invasion experiments.

Abstract: A driving circuit and a display panel are provided. The driving circuit includes a plurality of driving units which are cascaded. An Nth stage driving unit includes: a pull-up control module; a first bootstrap module; a pull-up module; a pull-down control module; and a first pull-down module. The driving circuit can be normally operated by input signal lines including a first clock signal line, a second clock signal line, a first power signal line, a second power signal line, and an initial signal line, so that types and a number of the input signal lines can be effectively reduced.

Abstract: A display panel integrated with a gate driving circuit in a display area is provided. In the display panel, gate driving signal lines and data lines are not arranged side by side between any same adjacent two columns of sub-pixels. This avoids possibility of arranging the data lines and the gate driving signal lines side by side between any same adjacent two columns of sub-pixels, prevents the data lines from being easily disturbed by a parasitic capacitance generated between the data lines and the gate driving signal lines, and also avoids abnormal images on the display panel.

Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.