Abstract: A terrestrial/satellite set-top-box (STB) system is provided. The system includes a handheld device and an STB. The handheld device has a built-in interactive application program. The STB includes a docking station and a playing circuit. The docking station carries the handheld device. The handheld device can be used for setting or remotely controlling the STB. The STB is linked to a wireless network via the handheld device so as to play movies and news programs from the network. The invention can solve the disadvantage of failing wirelessly to link network in the prior art.

Abstract: A television tuner employs a triple-conversion architecture to translate VHF/UHF TV signals to various standard IF frequencies. The television tuner includes a harmonic rejection mixer, a first image rejection mixer and a second image rejection mixer. The television tuner receives a television signal. The harmonic rejection mixer up-converts the television signal into a first IF signal according to a first reference signal with a fixed frequency. The first image rejection mixer further up-converts the first IF signal into a second IF signal according to a second reference signal with a tunable frequency. The second image rejection mixer down-converts the second IF signal into a third IF signal according to a third reference signal with a tunable frequency.

Abstract: A television tuner employs a single down-conversion architecture to translate VHF/UHF TV signals to various standard IF frequencies. The television tuner includes a harmonic rejection and quadrature mixer and a quadrature mixer. The harmonic rejection and quadrature mixer mixes a first-band signal with a reference signal to output a first pair of in-phase and quadrature-phase signals with a harmonic-frequency component eliminated from the resulting signals. A quadrature mixer mixes a second-band signal with the reference signal to output a second pair of in-phase and quadrature-phase signals. A digital signal processing circuit coupled to both the harmonic rejection and quadrature mixer and the quadrature mixer for selectively processing either the first pair of in-phase and quadrature-phase signals or the second pair of in-phase and quadrature-phase signals to generate an output signal corresponding to a desired channel.

Abstract: A television tuner employs a double quadrature mixing architecture to frequency-translate VHF/UHF TV signals to various standard IF frequencies. In the television tuner, a quadrature mixer converts the input television signal into a first in-phase signal and a first quadrature-phase signal according to a first reference signal, and a double quadrature mixer converts the first in-phase signal and first quadrature-phase signal into a second in-phase signal and a second quadrature-phase signal according to a second reference signal, and a polyphase filter filters the second in-phase signal and second quadrature-phase signal to produce an output signal.

Abstract: A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost.

Abstract: A fingerprint sensing circuit for detecting a fingerprint of a user, including a signal source, at least a sensing unit, a resistor, an electrode, and a detecting circuit. The signal source provides a reference signal. The electrode is coupled to a reference level. The sensing unit generates a sensed value according to the electrode and the fingerprint of the user. The resistor is coupled between the signal source and the output node. The detecting circuit is coupled to the output node. The resistor, the sensing unit, and the electrode constitute a filter circuit to the signal source. At least a first signal is generated to the output node according to the reference signal and the sensed value, and the detecting circuit detects the first signal to generate a corresponding detected result indicative of the fingerprint.

Abstract: An anticipative recursively-adjusting co-allocation mechanism (ARAM) includes the steps of: measuring a transmission bandwidth of a candidate server by a bandwidth measurement module; referring to the transmission bandwidth to calculate a recursive parameter value, and calculating a desired allocating file size of present round according to the recursive parameter value and an unassigned file size; allocating the desired allocating file size to the candidate server according to the transmission bandwidth and a transmission completion percentage of the candidate server at a previous round; performing the transmission and calculating the transmission completion percentage of each candidate server; examining the transmission completion percentage of the candidate sever; and examining whether or not an allocation of files is completed if any candidate server has completed a transmission, and looping to the next round if the file allocation has not been completed so as to enhance the data transmission performance

Abstract: A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Abstract: A mixer includes a transduction circuit, a first and a second switch circuit, and a first and a second load circuit. The transconductor circuit is for generating a differential current signal according to a differential voltage signal. The first switch circuit and the first load circuit are connected in series, and the first switch circuit is used to regulate the differential current signal in response to a first oscillator signal. The second switch circuit and a second load circuit are connected in series, and the second switch circuit is used to regulate the differential current signal in response to a second oscillator signal. The first load circuit and the second load circuit are connected at a common node to reduce harmonic interferences.

Abstract: A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost.

Abstract: A mixer with high linearity and a low operating voltage is provided. The mixer includes a transconductor and a switch circuit. The transconductor receives a differential voltage signal and outputs a differential current signal accordingly. The transconductor includes a first resistor, a second resistor, a differential amplifier, a first current source and a second current source. The switch circuit includes a first switch, a second switch, a third switch, and a fourth switch. The first and second switches are coupled to a first input of the differential amplifier, while the third and fourth switches are coupled to a second input of the differential amplifier. The first and third switches are mutually coupled to provide an output of the mixer, while the second and fourth switched are mutually coupled to provide another output of the mixer. Each of the first, second, third and fourth switches determines whether to allow the differential current signal to pass through according to a differential control signal.

Abstract: A method and an apparatus utilizing the RFID technology for the login security of a computing device are disclosed. The computing device includes a processing unit, an RFID reader, and a memory. The RFID reader is coupled to the processing unit for communicating with an external RFID tag in which a user data is stored. The memory is coupled to the processing unit for storing a login data. The RFID reader reads the user data from the RFID tag and the processing unit compares the user data with the login data. If the user data matches the login data, the processing unit allows the computing device to be accessed.

Abstract: A hybrid Global Positioning System (GPS) receiving method, and associated GPS receiving apparatus is provided. The GPS receiving apparatus includes an RF front-end circuit, a correlation circuit, an acquisition engine and a bidirectional interface control unit. The RF front-end receiving circuit receives a satellite signal and converts the same into a baseband signal. The acquisition engine, coupled to the correlation circuit, determines reception power of the GPS satellite signal. The interface control unit, coupled to the acquisition engine, provides a low-speed interface for transmitting GPS intermediate data that includes a code bin, a frequency bin, navigation data, a local system time and a GPS time. The interface control unit includes a memory interface unit for coupling to a memory.

Abstract: The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

Abstract: A mixer includes a transduction circuit, a first and a second switch circuit, and a first and a second load circuit. The transconductor circuit is for generating a differential current signal according to a differential voltage signal. The first switch circuit and the first load circuit are connected in series, and the first switch circuit is used to regulate the differential current signal in response to a first oscillator signal. The second switch circuit and a second load circuit are connected in series, and the second switch circuit is used to regulate the differential current signal in response to a second oscillator signal. The first load circuit and the second load circuit are connected at a common node to reduce harmonic interferences.

Abstract: An anticipative recursively-adjusting co-allocation mechanism (ARAM) includes the steps of: measuring a transmission bandwidth of a candidate server by a bandwidth measurement module; referring to the transmission bandwidth to calculate a recursive parameter value, and calculating a desired allocating file size of present round according to the recursive parameter value and an unassigned file size; allocating the desired allocating file size to the candidate server according to the transmission bandwidth and a transmission completion percentage of the candidate server at a previous round; performing the transmission and calculating the transmission completion percentage of each candidate server; examining the transmission completion percentage of the candidate sever; and examining whether or not an allocation of files is completed if any candidate server has completed a transmission, and looping to the next round if the file allocation has not been completed so as to enhance the data transmission performance

Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal.

Abstract: A sigma-delta modulator includes a loop filter, a single bit quantizer, a single bit DAC, an adder. The loop filter is for filtering a summed signal to generate a filtered signal. The single bit quantizer is coupled to the loop filter, for performing a quantization process to the filtered signal to generate a quantized signal. The single bit DAC is coupled to the single bit quantizer, has an adjustable configuration, and is for generating a feedback signal according to the quantized signal and the configuration thereof. The adder is coupled to the loop filter and the single bit DAC, for summing an input signal and the feedback signal to generate the summed signal.

Abstract: A hybrid Global Positioning System (GPS) receiving method, and associated GPS receiving apparatus is provided. The GPS receiving apparatus includes an RF front-end circuit, a correlation circuit, an acquisition engine and a bidirectional interface control unit. The RF front-end receiving circuit receives a satellite signal and converts the same into a baseband signal. The acquisition engine, coupled to the correlation circuit, determines reception power of the GPS satellite signal. The interface control unit, coupled to the acquisition engine, provides a low-speed interface for transmitting GPS intermediate data that includes a code bin, a frequency bin, navigation data, a local system time and a GPS time. The interface control unit includes a memory interface unit for coupling to a memory.

Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal.