Patents by Inventor Chao-Wei Tseng

Chao-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11933809
    Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: March 19, 2024
    Assignee: SENSORTEK TECHNOLOGY CORP.
    Inventors: Shih-Wei Lee, Chia-Hao Lin, Shih-Hsiung Tseng, Kuan-Ju Tseng, Chao-Shiun Wang
  • Patent number: 11722058
    Abstract: An emulated current generation circuit of a power converting circuit, providing an emulated current includes an AC component current and a DC component current, includes a first current circuit, a second current circuit, a combination circuit and a calibration circuit. The first current circuit generates a ramp signal as the AC component current. The second current circuit is coupled to an output stage of power converting circuit to provide a sensing current. The DC component current is generated after performing a sample-and-hold processing on the sensing current. The combination circuit is coupled to the first current circuit and second current circuit respectively to combine the AC component current and DC component current into an emulated sensing current. The calibration circuit is coupled to the first current circuit, second current circuit and combination circuit to dynamically adjust the ramp signal according to the emulated sensing current and sensing current.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: August 8, 2023
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Chao-Wei Tseng, Yow-Tsyr Liang
  • Publication number: 20210328509
    Abstract: An emulated current generation circuit of a power converting circuit, providing an emulated current includes an AC component current and a DC component current, includes a first current circuit, a second current circuit, a combination circuit and a calibration circuit. The first current circuit generates a ramp signal as the AC component current. The second current circuit is coupled to an output stage of power converting circuit to provide a sensing current. The DC component current is generated after performing a sample-and-hold processing on the sensing current. The combination circuit is coupled to the first current circuit and second current circuit respectively to combine the AC component current and DC component current into an emulated sensing current. The calibration circuit is coupled to the first current circuit, second current circuit and combination circuit to dynamically adjust the ramp signal according to the emulated sensing current and sensing current.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 21, 2021
    Inventors: CHAO-WEI TSENG, YOW-TSYR LIANG
  • Patent number: 8766357
    Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Tseng, Kun-Ming Huang, Cheng-Chi Chuang, Fu-Hsiung Yang
  • Publication number: 20130228873
    Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Tseng, Kun-Ming Huang, Cheng-Chi Chuang, Fu-Hsiung Yang
  • Patent number: 8340320
    Abstract: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: December 25, 2012
    Assignee: Mediatek Inc.
    Inventor: Chao-Wei Tseng
  • Patent number: 8174071
    Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: May 8, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: William Wei-Yuan Tien, Chao-Wei Tseng, Fu-Hsin Chen
  • Publication number: 20100128886
    Abstract: Mute circuits capable of eliminating audible noise when the audio system is powered up and powered down are disclosed. A discharge element is coupled between an audio processing unit and an audio output unit in an audio system and a mute control unit is coupled to the discharge element. The mute circuit comprises an active element comprising a control terminal coupled to at least one power voltage at a power terminal of a functional element in the audio processing unit through a capacitor and turning on, by AC capacitor coupling, to drive the discharge element when the audio system is powered up, such that the discharge element is turned on to discharge an output current of the audio processing unit to a ground terminal, thereby muting the audio output unit to eliminate audible noise.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 27, 2010
    Applicant: MEDIATEK INC.
    Inventor: Chao-Wei TSENG
  • Publication number: 20090273029
    Abstract: An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: William Wei-Yuan Tien, Chao-Wei Tseng, Fu-Hsin Chen
  • Publication number: 20090236707
    Abstract: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.
    Type: Application
    Filed: May 28, 2009
    Publication date: September 24, 2009
    Applicant: MEDIATEK INC.
    Inventors: Nan-Cheng Chen, Chun-Wei Chang, Chao-Wei Tseng
  • Publication number: 20080080142
    Abstract: An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: April 3, 2008
    Applicant: MEDIATEK INC.
    Inventors: Nan-Cheng Chen, Chun-Wei Chang, Chao-Wei Tseng