Patents by Inventor Chao-Yi Cho

Chao-Yi Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929561
    Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: I-Shu Lee, Chih-Hung Cho, Hau Yuen Tan, Chien-Yi Wu, Po-Sheng Chen, Chao-Hsu Wu, Yi Chen, Hung-Ming Yu, Chih-Chien Hsieh
  • Patent number: 8643751
    Abstract: A method for detecting dead pixels obtains a downsampling set formed by a plurality of sample pixels by downsampling a to-be-tested image, and computes a moving average for each sample pixel to determine whether the sample pixel is a dead pixel candidate. If so, all pixels in a neighborhood of the dead pixel candidate are determined as to-be-detected pixels. For each to-be-detected pixel, a compensated value and a weighted average under a mask are estimated. A hypothetic dead pixel value is obtained by comparing an original pixel value of each to-be-detected pixel and the moving average of the dead pixel candidate. Whether the to-be-detected pixel is a dead pixel is determined by using the original pixel value, the compensated value, the weighted average and the hypothetic dead pixel value.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: February 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Yi Cho, Tse-Min Chen
  • Publication number: 20130141595
    Abstract: A method for detecting dead pixels obtains a downsampling set formed by a plurality of sample pixels by downsampling a to-be-tested image, and computes a moving average for each sample pixel to determine whether the sample pixel is a dead pixel candidate. If so, all pixels in a neighborhood of the dead pixel candidate are determined as to-be-detected pixels. For each to-be-detected pixel, a compensated value and a weighted average under a mask are estimated. A hypothetic dead pixel value is obtained by comparing an original pixel value of each to-be-detected pixel and the moving average of the dead pixel candidate. Whether the to-be-detected pixel is a dead pixel is determined by using the original pixel value, the compensated value, the weighted average and the hypothetic dead pixel value.
    Type: Application
    Filed: May 18, 2012
    Publication date: June 6, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Yi CHO, Tse-Min CHEN
  • Patent number: 7398499
    Abstract: A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. ?1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: July 8, 2008
    Assignee: Chang Gung University
    Inventors: Ming-Hong Lai, Chao-Yi Cho, Chia-Chi Chu, Wu-Shiung Feng
  • Publication number: 20070277138
    Abstract: A new method of searching paths that are suffering ESD is proposed in this invention, improving the design flow of a VLSI circuit and reducing the cost of designing the ESD circuits in a whole chip, comprising three parts, the circuit flattening, the closure algorithm, and the supernode algorithm. The objective is to find the paths satisfying the following two constraints: (1) only one edge connected to the gate pin and the source (or drain) pin is allowed; (2) only the head-node and the tail-node in a path could be the pin of top-level circuit. Two algorithms in this invention are the closure algorithm that uses the closure property in the ?1/0/1 matrix multiplication so that the connective property of nodes can be observed after several matrix self-multiplication, and the supernode algorithm.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 29, 2007
    Applicant: CHANG GUNG UNIVERSITY
    Inventors: Ming-Hong Lai, Chao-Yi Cho, Chia-Chi Chu, Wu-Shiung Feng