Abstract: A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.

Abstract: In at least one embodiment, a read operation in a data storage system having lossy storage media includes fetching target data of the read operation from a lossy storage device into a buffer, transferring the target data from the buffer to an external controller external to the lossy storage device via a communication bus, performing error location processing on the target data during the transferring of the target data, communicating error location information regarding at least one error location to error repair logic via the communication bus, the error repair logic repairing the at least one error in the target data using the error location information, and the external controller causing the target data as repaired to be transmitted toward a destination. By deserializing the suboperations comprising the read operation, read latency can be reduced.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: A computer-implemented method for performing a voltage-based measurement of a resistive memory cell having a plurality of programmable cell states includes providing, via a processor, a prebiased voltage at a connecting node. The method further includes prebiasing a bitline capacitance of the resistive memory cell. In other aspects, the method includes settling, via the processor, a sensing circuit to a target voltage. The method further includes outputting a resultant value based on a sensed voltage at the resistive memory cell.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: In at least one embodiment, a controller of a non-volatile memory array retires physical pages within the non-volatile memory array on a page-by-page basis. The physical pages retired by the controller include a first physical page sharing a common set of memory cells with a second physical page. While the first physical page is retired, the controller retains the second physical page as an active physical page, writes dummy data to the first physical page, and writes data received from a host to the second physical page.

Abstract: A data storage device for storing N-symbol codewords.

Abstract: A method, according to one embodiment, includes repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: receiving a compressed logical page of data, finding an open codeword having an amount of available space which is greater than or equal to a size of the compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. The compressed logical page does not straddle out of the open codeword. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In a data storage system including a non-volatile memory array, a controller repeatedly determines at least one health metric of the non-volatile memory array during an operating lifetime of the non-volatile memory array. In response to determining the at least one health metric, the controller selectively varies an erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array, such that endurance of the non-volatile memory array is improved.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: A method for read measurement of a plurality N of resistive memory cells having a plurality M of programmable levels is suggested. The method includes a step of reading back from a number of reference cells to obtain a reading back parameter, a step of determining an actual read voltage for the N memory cells based on the obtained reading back parameter for obtaining a target read current at a following read measurement, and, a step of applying the determined actual read voltage to the N memory cells at the following read measurement.

Abstract: A method for conditioning at least one Phase Change Memory, PCM, cell. The PCM cell is characterized by a number of pre-defined characteristics or properties. For pre-conditioning, at least one conditioning pulse is applied to the PCM such that at least one selected characteristic of the number of pre-defined characteristics is changed to a desired value.

Abstract: In at least one embodiment, a controller of a non-volatile memory array determines, for each of a plurality of regions of physical memory in the memory array, an associated health grade among a plurality of health grades and records the associated health grade. The controller also establishes a mapping between access heat and the plurality of health grades. In response to a write request specifying an address, the controller selects a region of physical memory to service the write request from a pool of available regions of physical memory based on an access heat of the address and the mapping and writes data specified by the write request to the selected region of physical memory.

Abstract: A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.

Abstract: A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.

Abstract: In some aspects, a computer-implemented method for performing a voltage-based measurement of a resistive memory cell includes a plurality m of programmable cell states. The method may include providing, via a processor, a prebiased voltage at a connecting node coupled to the resistive memory cell, coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit, prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit, settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell, sensing a voltage of the resistive memory cell, and outputting a resultant value based on the sensed voltage.

Abstract: A set of K prefix codes for use in pseudo-dynamic compression are determined by seeding each of K clusters with a respective one of K data pages selected from a training data set, where K is a positive integer greater than 1. For each of the K randomly selected data pages, a prefix code is determined for its cluster utilizing Huffman encoding. Each remaining data page of the training data set is assigned to one of the K clusters whose prefix code yields the highest compression ratio. For each of the K clusters, the prefix code is updated by performing Lempel-Ziv (LZ) encoding on all pages assigned to that cluster, forming a sequence from results of the LZ encoding, and extracting an updated prefix code for the cluster from the sequence utilizing Huffman encoding. The set of K prefix codes determined for the K clusters is then output.