Abstract: The present invention is a wavelength division multiplexing (WDM)/code division multiple access (CDMA) hybrid code fiber optic communication device. It provides multiple, concurrent, asynchronous, bursty communication at up to full data rate at each port. The invention includes a novel physical channel scrambling technique which allows coders and decoders to conveniently select any encoded channel and increases the communications throughput. This hybrid approach combines WDM with a form of space/time division multiplexing (matrix codes) applied to each data bit so that up to P channels can be defined and simultaneously used without having the stringent hardware requirements for P different wavelengths or P different time slots. To alleviate cross-channel interference that can produce an error rate limitation in both optical matrix CDMA and WDM/CDMA Hybrid codes, a modification of this invention has been designed.

Abstract: The present invention is a compact, quantized, photonic delay-line array based on nested, generalized, spirals. The array includes N optical waveguides and is quantized in that consecutive waveguides can have their delays differ by the same delay difference design constant, D. Thus the delay for the n.sup.th delay line can be expressed as D.sub.n =D.sub.0 +n*D where D.sub.0 is the delay through the first waveguide and n=0, 1, 2, . . . ,(N-1). The arrays can be formed on a suitable substrate by a process permitting crossovers such as silica-on-silicon or optical polymer planar lightwave circuits. The nested waveguides are applied as single turn or multiturn generalized spirals with either sharp (mirrored) or rounded corners. The approach is scalable because N may range from 2 to over 64, limited only by the wafer (substrate) material and size, or D may range from a picosecond to well over a nanosecond with currently available substrates.

Abstract: A three-state driver circuit including a first gating circuit responsive to a first enable signal for selectively gating an input signal to provide a first gated signal at an internal node, a second gating means responsive to a second enable signal and connected to the internal node for selectively gating the first gated signal so as to provide the output of the three-state bus driver, and a testing circuit for detecting or controlling the state of the internal node, and for providing a test output indicative of the inoperability of the first or second gating circuit.

Abstract: The electronic package (10) is comprised of a plurality of support plates (12-24), each of which has a plenum therein and preferably webs extending into the plenum for fluid flow control and heat transfer. A wafer (104) is mounted in a recess (100) in the support plate (12) so that fluid in the plenum (52) directly cools the wafer. Electrical connection is by flexible cable (108) to an exterior printed wiring board (40). The package may have any selected number of support plates, and each support plate may carry one full-sized wafer for compact packaging.

Abstract: A "cooperative-word" linear array parallel processor comprises many logically identical memory words or micro-processors ordered in a linear array by a Chaining channel. Inasmuch as the Chaining channel can contain different information (either data to be processed or control information) at each word position, it permits highly parallel word-cooperative operations such as pair-wise arithmetic. The processor also has several global communication channels in which data may be transferred between an external buffer and a specified subset of processor words. Inasmuch as individual words may be addressed by their content rather than by their physical locations, relatively simple switching logic within each word provides effective self-repair. A plurality of flag flip-flops in each individual cell interact with gobal control lines to activate processing within a particular cell and to indicate the results of operations performed by that cell.