Abstract: Some embodiments are directed to a keyed message authentication code (MAC) device (100) for computing a keyed MAC for an input message using encoded representations. The keyed MAC device may be configured to apply a sequence of compressions functions, at least one of which takes a state as input in an encoded representation.

Abstract: Some embodiments are directed to a compiling device (100) configured for selecting of protective transformations to improve security of a computer program. The compiling device is configured to assign protective transformations to parts of the data flow graph, and obtain a compilation of the computer program representation from at least the data flow graph and the assigned protective transformations which satisfy the security and/or the performance target.

Abstract: Some embodiments are directed to a compiler device (400) arranged for obfuscation of a computer program. The compiler device performs a live variable analysis on the computer program representation, and modifies the computer program representation to encode a first variable using at least a second variable as an encoding parameter.

Abstract: Some embodiments are directed to a compiler device (400) arranged for obfuscation of a computer program. The compiler device performs a live variable analysis on the computer program representation, and modifies the computer program representation to encode a first variable using at least a second variable as an encoding parameter.

Abstract: A compiling device (100) configured to convert a source code computer program (102) into an object code computer program (106), the compiling device comprising—a processor circuit arranged to—parse (120) the source code computer program and generate a static single assignment (SSA) graph (122) for at least a portion of the source code computer program, and—search for a second subgraph (P) of the SSA graph, wherein a first subgraph (N) is a subgraph of the second subgraph (N?P), a sum of the bit sizes associated to incoming edges of the second subgraph being smaller than a sum of the bit sizes associated to incoming edges of the first graph, —implementing the second subgraph of the SSA graph in the object code computer program as a single operation thus omitting the assignments corresponding to edges of the first subgraph.

Abstract: Some embodiments are directed to a compiler device (100) configured to identify a sub-graph (210) in a data flow graph having one or more output nodes marked as encoded and one or more output nodes marked as non-encoded, and to replace the sub-graph by an encoded first sub-graph (210.1), and a non-encoded second sub-graph (210.2), wherein the first sub-graph has only encoded output nodes, and the second sub-graph has only non-encoded output nodes.

Abstract: A compiling device (100) configured to convert a source code computer program (102) into an object code computer program (106), the compiling device comprising —a processor circuit arranged to —parse (120) the source code computer program and generate a static single assignment (SSA) graph (122) for at least a portion of the source code computer program, and —search for a second subgraph (P) of the SSA graph, wherein a first subgraph (N) is a subgraph of the second subgraph (N?P), a sum of the bit sizes associated to incoming edges of the second subgraph being smaller than a sum of the bit sizes associated to incoming edges of the first graph, —implementing the second subgraph of the SSA graph in the object code computer program as a single operation thus omitting the assignments corresponding to edges of the first subgraph.

Abstract: Some embodiments are directed to a compiling device (100) configured for selecting of protective transformations to improve security of a computer program. The compiling device is configured to assign protective transformations to parts of the data flow graph, and obtain a compilation of the computer program representation from at least the data flow graph and the assigned protective transformations which satisfy the security and/or the performance target.

Abstract: Some embodiments are directed to a keyed message authentication code (MAC) device (100) for computing a keyed MAC for an input message using encoded representations. The keyed MAC device may be configured to apply a sequence of compressions functions, at least one of which takes a state as input in an encoded representation.

Abstract: Some embodiments are directed to a compiler device (100) configured to identify a sub-graph (210) in a data flow graph having one or more output nodes marked as encoded and one or more output nodes marked as non-encoded, and to replace the sub-graph by an encoded first sub-graph (210.1), and a non-encoded second sub-graph (210.2), wherein the first sub-graph has only encoded output nodes, and the second sub-graph has only non-encoded output nodes.

Abstract: A cryptographic device (200) is provided to compute a key dependent cryptographic function for an input message. The cryptographic device has a data store arranged to store multiple variables (w) on which the cryptographic device acts to compute the cryptographic function, a variable (w) being distributed over multiple shares (wj) and represented in the data store as multiple encoded shares (xj), an encoded share being an encoding (xj=Encj (wj, sj)) of a share (wj) together with a state (sj), the multiple states (sj) corresponding to the same variable (w) having a relationship with the input message (M) so that there exists an injective mapping (?) from the input message (M) to the multiple states (?(M)=(s0, . . . , sn?1)).

Abstract: A cryptographic device (200) is provided to compute a key dependent cryptographic function for an input message. The cryptographic device has a data store arranged to store multiple variables (w) on which the cryptographic device acts to compute the cryptographic function, a variable (w) being distributed over multiple shares (wj) and represented in the data store as multiple encoded shares (xj), an encoded share being an encoding (xj=Encj (wj, sj)) of a share (wj) together with a state (sj), the multiple states (sj) corresponding to the same variable (w) having a relationship with the input message (M) so that there exists an injective mapping (?) from the input message (M) to the multiple states (?(M)=(s0, . . . , sn?1)).

Abstract: In an aspect, an enclosure member for a circuit board includes first, second, third, fourth and fifth walls that define an interior. The first and second walls face each other. The third and fourth walls face each other. The fifth wall faces an opening. The first and second support members face the second wall. The second support member is spaced longitudinally from the first support member. The first and second walls are spaced apart by a distance that increases towards the opening. Any surfaces in the interior that at least partially face the second wall have a distance from the second wall that does not decrease towards the opening. The interior is free of surfaces that face the fifth wall and are perpendicular to the second wall thereby preventing die lock during molding, while providing the enclosure member with first and second support members that are spaced longitudinally.

Abstract: Unauthorized use of computer programs is made difficult by compiling a processor rather than just compiling a program into machine code. The way in which the processor should respond to machine instructions, i.e. its translation data, is computed from an arbitrary bit string B and a program P as inputs. The translation data of a processor are computed that will execute operations defined by the program P when the processor uses the given bit string B as a source of machine instructions. A processor is configured so that it will execute machine instructions according to said translation data. Other programs P? may then be compiled into machine instructions B? for that processor and executed by the processor. Without knowledge of the bit string B and the original program P it is difficult to modify the machine instructions B? so that a different processor will execute the other program P?.

Abstract: In an aspect, an enclosure member for a circuit board includes first, second, third, fourth and fifth walls that define an interior. The first and second walls face each other. The third and fourth walls face each other. The fifth wall faces an opening. The first and second support members face the second wall. The second support member is spaced longitudinally from the first support member. The first and second walls are spaced apart by a distance that increases towards the opening. Any surfaces in the interior that at least partially face the second wall have a distance from the second wall that does not decrease towards the opening. The interior is free of surfaces that face the fifth wall and are perpendicular to the second wall thereby preventing die lock during molding, while providing the enclosure member with first and second support members that are spaced longitudinally.

Abstract: Unauthorized use of computer programs is made difficult by compiling a processor rather than just compiling a program into machine code. The way in which the processor should respond to machine instructions, i.e. its translation data, is computed from an arbitrary bit string B and a program P as inputs. The translation data of a processor are computed that will execute operations defined by the program P when the processor uses the given bit string B as a source of machine instructions. A processor is configured so that it will execute machine instructions according to said translation data. Other programs P? may then be compiled into machine instructions B? for that processor and executed by the processor. Without knowledge of the bit string B and the original program P it is difficult to modify the machine instructions B? so that a different processor will execute the other program P?.

Abstract: In a system, a server provides a digital signal processing function ƒ to an executing device in an obfuscated form. The function ƒ includes a function cascade of signal processing functions ƒi, 1?i?N (e.g., FC1(x)?ƒN? . . . ?ƒ1(x)). The server includes a processor for selecting a set of 2N invertible permutations pi, 1?i?2N; calculating a set of N functions gi, where gi is functionally equivalent to p2i?1?ƒi?p2i?1, for 1?i?N; and calculating a set of N?1 functions hi, where hi is functionally equivalent to p2i?1?1?p2i?2, for 2?i?N. The server equips the executing device with an execution device function cascade that includes yN?hN?yN?1?hN?1? . . . ?y1, where y1, . . . , yN are function parameters (e.g., ED1(y1, . . . , yN)?yN?hN?yN?1?hN?1? . . . ?y1), and provides the functions g1, . . . gN to the executing device. The executing device obtains the functions g1, . . .

Abstract: In a system, a server provides a digital signal processing function ƒ to an executing device in an obfuscated form. The function ƒ includes a function cascade of signal processing functions ƒi, 1?i?N (e.g., FC1(x)?ƒN? . . . ?ƒ1(x)). The server includes a processor for selecting a set of 2N invertible permutations pi, 1?i?2N; calculating a set of N functions gi, where gi is functionally equivalent to p2i?1?ƒi?p2i?1, for 1?i?N; and calculating a set of N?1 functions hi, where hi is functionally equivalent to p2i?1?1?p2i?2, for 2?i?N. The server equips the executing device with an execution device function cascade that includes yN?hN?yN?1?hN?1? . . . ?y1, where y1, . . . , yN are function parameters (e.g., ED1(y1, . . . , yN)?yN?hN?yN?1?hN?1? . . . ?y1), and provides the functions g1, . . . gN to the executing device. The executing device obtains the functions g1, . . .

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC0, UC1, UC2, UC3), wherein each issue slot comprises a plurality of functional units (FU20, FU21, FU22). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC4) arranged for loading an immediate value (IMV1) in dependence upon a dedicated instruction (IMM).