Patents by Inventor Charles A. Moorwood

Charles A. Moorwood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9065747
    Abstract: A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 23, 2015
    Assignee: Infinera Corp.
    Inventors: Jan Bialkowski, Charles A. Moorwood
  • Publication number: 20140186034
    Abstract: A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Infinera Corp.
    Inventors: Jan Bialkowski, Charles A. Moorwood
  • Patent number: 5430726
    Abstract: A repeater interface controller receives a data packet at one of a plurality of port nodes from an associated segment of a local area network. The plurality of port nodes determine a priority port node when more than one port node receives a data packet at substantially the same time. The priority port node transmits the data packet from the priority port node to a central node. The central node receives the data packet from the priority node, repeats the data packet, and transmits the repeated data packet to the non-priority port nodes. Each non-priority port node receives the repeated data packet and transmits the repeated data onto its associated segment. Management and status information is transferred between the port nodes and an external processor and an external display by an internal bus and an external bus. A bus arbiter alternately provides a bus controller and the external controller control of both the internal and external buses to transfer the data.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: July 4, 1995
    Inventors: Charles A. Moorwood, Charan J. Singh
  • Patent number: 5396495
    Abstract: The present invention is directed to various features of a repeater interface controller (RIC) that connects segments of a bus/tree local area network. In the described embodiment of the invention, the RIC implements the IEEE 802.3 repeater specification.In accordance with another aspect of the present invention, the RIC provides hub management support in the form of information regarding the status of its ports and of the packets it is repeating. This data is available in three forms: counted events, recorded events and status packets. This information is available through the RIC's interface. The counters and event recording registers have user-definable masks which enable them to be configured to count and record a variety of events.In accordance with another aspect of the present invention, the RIC management statistics at maximum network bandwidth. Statistics are logged while a packet repetition is in process and are furnished to counter and flag arrays after transmission of the same packet has ended.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: March 7, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Moorwood, Charan J. Singh, Daniel J. Cimino, Howard Quoc Vo
  • Patent number: 5384767
    Abstract: The nodes of a repeater interface controller which repeats data packets received from one segment of a local area network onto the remaining segments of the local area network include loopback circuitry that allow the data packets received from the one segment to be repeated back onto the one segment in addition to the remaining segments of the local area network, thereby allowing the integrity of the one segment to be verified.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: January 24, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Moorwood, Charan J. Singh, Dennis E. Holland, Daniel J. Cimino, Howard Q. Vo, Vickie M. Yeung, David Crosbie, Haresh K. Shah
  • Patent number: 5293375
    Abstract: A repeater interface controller receives a data packet at one of a plurality of port nodes from an associated segment of a local area network. The port nodes determine a priority port node, if more than one port node receives a data packet at substantially the same time, and transmit the data packet from the priority port node to a central node. The central node receives the data packet, repeats the data packet from the priority node, and transmits the repeated data packet to the non-priority port nodes. Each non-priority port node receives the repeated data packet and transmits the repeated data onto its associated segment. Each port node further includes a partitioning port state machine which monitors its associated segment and partitions the segment from the repeater interface controller when the partitioning port state machine detects a collision in a predetermined number of consecutive data packets.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: March 8, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Moorwood, Charan J. Singh, Dennis E. Holland, Daniel J. Cimino, Howard Q. Vo, Vickie M. Yeung, David Crosbie, Haresh K. Shah