Abstract: A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with he particular DAL.

Abstract: A methodology for selecting an optimal group of flip-flops in a circuit design to be converted into BIST elements is disclosed which minimizes the performance degradation resulting from such conversion. In accordance with the present invention, the additional timing delays introduced into the circuit design resulting from each conversion of a flip-flop into a BIST element is incorporated into the selection of those flip-flops to be converted such that only those flip-flops which may be converted without any resultant timing violations are deemed suitable for conversion. A minimum group of these "suitable" flip-flops which breaks all of the logic cycles in the circuit is then selected for BIST conversion. Thus, selection methodologies in accordance with the present invention not only simultaneously minimizes the increase in silicon area due to BIST conversion while maximizing fault coverage, but also results in minimal performance degradation.