Abstract: A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.

Abstract: A neutron detector array is capable of measuring a wide range of neutron fluxes. The array includes multiple semiconductor neutron detectors. Each detector has a semiconductor active region that is resistant to radiation damage. In one embodiment, the array preferably has a relatively small size, making it possible to place the array in confined locations. The ability of the array to detect a wide range of neutron fluxes is highly advantageous for many applications such as detecting neutron flux during start up, ramp up and full power of nuclear reactors.

Abstract: A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region vertically spaced from the source region by a drift layer. The pitch distance p between gate regions is 1 to 5 microns and the drift layer thickness d is also 1 to 5 microns.In one embodiment the source regions are positioned alternatively with the gate regions and are formed in a top layer of high doping concentration. In another embodiment the gate regions are ion implanted in the layer arrangement.In another embodiment the structure includes a dual oxide layer covering gate and source or drain regions, and in yet another embodiment contacts for the drain, source and gate regions are located on the same side of the substrate member.

Abstract: A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends along a bottom of a recess between the mesas and along a side of each of the mesas forming the recess. The gate contact also extends along a portion of the top surface of each of the mesas. In one embodiment of the invention, a notch is formed in the top surface of the mesas between the gate contact and the heavily doped region.

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Abstract: A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.