Abstract: The present invention relates to a tone signal generator. The tone signal generator includes first tone signal generation means for producing a dual-tone, multi-frequency ("DTMF") audio signal; second tone signal means for producing a plurality of non-DTMF audio signals; storage means for storing data that represents at least one channel of an output audio tone signal; and selection means for selectively loading the DTMF signal into the storage means and for selectively accumulating the non-DTMF signals into the storage means so as to generate the output tone signal.

Abstract: The output gates of a delta-sigma modulator can generate i(t) transient signal in the power supply lines of a delta-sigma modulator. These i(t) spikes, which would otherwise produce non-linearities which can be coupled into the frequency band of interest of the modulator, are made to be linear by using return-to-zero data encoding and by providing multi-bit outputs to the delta-sigma modulator in which the output states all have equal numbers of logic ones at the output lines for each of the output states.

Abstract: The thermal noise generated through the feedback capacitor of a delta-sigma modulator is attenuated by transferring a reference voltage through the capacitor in two separate steps during each sampling period. This permits a reduction in the size of the feedback capacitor, thereby reducing thermal noise, without increasing the voltage on the switching capacitors on the summing node side of the feedback capacitors which would induce degradation due to hot electron effects.

Abstract: An analog-to-digital converter includes a two-bit delta-sigma modulator. The delta-sigma modulator is comprised of a first stage integrator (10) that feeds a noise shaping circuit (18). The output of the noise shaping circuit (18) is input to a two-threshold imbedded ADC (20) to provide the two-bit output. This output of the imbedded ADC (20) is input to a digital filter (22) to provide the filtered digital output, this filtering high-frequency noise. The output of the imbedded ADC (20) is also fed back through a three-level DAC (24) to a summing junction on the input of the integrator (10). The three-level DAC 24 has three states that are output with one state being a "do nothing" state. The thermal noise performance of the delta-sigma modulator as a function of the quantizer threshold voltages is first simulated and then the value of the quantizer thresholds selected to provide optimum signal-to-thermal noise performance.

Abstract: A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta.

Abstract: A analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), and A/D converter (18), an oscillator (12) and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.

Abstract: An oversampling analog-to-digital converter is responsive to an analog input signal for providing a digital output signal representative of the magnitude of the analog input signal at an output bus. The analog input signal is quantized through a sigma delta modulator stages for providing first and second digital output signals which are recombined through at least first and second digital integrators and at least first and second digital differentiators of a low pass comb filter for providing the digital output signal. The first digital output signal controls the application of either a digital correction signal or digital zeroes to the least significant portion of a predetermined number of accumulator cells of the first digital integrator thereby substituting the digital correction signal for the digital output signal to weight the latter's contribution and compensate for the quantization error which increases the resolution of the digital output signal.

Abstract: A technique for accomplishing a read, modify and write operation of a memory in a processor in a single cycle of the processor, where a cycle is understood as the time between successive loads of operands to the processor. A memory having two distinct portions of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or snake-like configuration. A decoder is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory.

Abstract: A digital correction signal is generated as a weighting actor for a first digital output signal applied to a digital integrator formed within a comb filter to compensate for gain mismatches between the stages of a sigma delta modulator and improve the resolution of the digital output signal at the output bus of an oversampling analog-to-digital converter. The current state the a first digital output signal provided at the output of one stage of the sigma delta modulator is compared with the previous state of the same signal. A detection signal is activated upon the occurrence of two consecutive states of the firrt digital output signal of the same level wherein such an occurrence corresponds to a noise spike in the digital output signal. The digital output signal is sampled during and after the spike, and the sampled values thereof are compared.

Abstract: A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

Abstract: A structure for implementing a plurality of independent filters, such as finite impulse response filters, in an efficient manner. Coefficient and data operands associated with each of the independent filters are stored in a predetermined order in a storage device and selectively coupled to an arithmetic unit for processing in a predetermined manner. Calculations for each filter are successively made and selectively stored. Although independent filters exist, processing circuitry is multiplexed and shared to substantially minimize associated control circuitry.

Abstract: A dissolving tank for dissolving a large amount of gas in a liquid and including a generally horizontally disposed tray (28) (29) mounted within the tank (2) (21) to divide the tank (2) (21) into an upper reaction zone (36) and a lower discharge zone (38). The tray (28) (29) has formed therein both a central opening (34) (35) for fluid communication between the discharge zone (38) and the reaction zone (36) and peripheral openings (32) (33) which allow any liquid which collects on the tray (28) (29) to flow from reaction zone (36) to discharge zone (38). The dissolving tank further includes liquid feed means (10) positioned within the tank (2) (21) below the tray (28) (29) to discharge liquid upwardly through the central opening (34) (35) of the tray (28) (29) and into the reaction zone (36). The dissolving tank further includes liquid distribution means (14) mounted within the tank (2) (21) above the tray (28) (29) and having flared sidewalls (15) and a vertically-oriented distribution orifice (16).

Abstract: Vanadium oxides are reduced to the metallic state by reaction with carbon in a plasma arc torch.

Abstract: Iron ore and a mixture of methane and hydrogen are fed into a plasma arc torch and form a swirling film of material that slowly descends the walls of the torch. The ore is reduced in the torch, and metallic iron is collected in a crucible below the torch.