Abstract: A high-speed low-power-consumption two-input arbiter circuit comprises two input inverters, two inverters cross-coupled to form a latch and two additional inverters that drive a difference detector. The detector responds only to a voltage difference on its inputs that exceeds a specified value. In this way, signals are blocked from appearing at the outputs of the detector while the latch is in a metastable state. Additionally, an n-input arbiter circuit comprises (n-1)+(n-2)+ . . . +[n-(n-1)] two-input arbiter circuits and logic circuitry connected to the outputs of the two-input circuits for supplying a priority signal to one and only one at a time of n output terminals of the n-input circuit.

Abstract: A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.