Abstract: On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.

Abstract: An infrared detection system is disclosed comprising a planar array segment of infrared detector elements, a multi-layer module and a buffer board disposed intermediate the detector array segment and the multi-layer module. The buffer board is disposed parallel to the planar array segment of detector elements and transverse to the plane of the module layers. The buffer board is disposed in abutting electrical connection with the detector elements and conductive patterns formed on the multi-layer module. The buffer board facilitates electrical communication between the detector elements and the module and conductive patterns formed on the module layers, and also enhances the structural characteristics and separate testability of the system components.

Abstract: An infrared focal plane module as disclosed for interfacing a plurality of detector elements to external electronics. The module comprises a plurality of integrated circuits disposed in substantially overlapping registry to form a module body, each of the integrated circuits is formed to include a layer of semi-conductive material such as silicon disposed upon a major surface of an insulating substrate, e.g. sapphire, to form electronic circuits. Each of the integrated circuits further includes conductive areas formed along first and second edge portions of the substrate to communicate electrical signals to and from the integrated circuit.

Abstract: A method and apparatus are disclosed for forming a high density multi-layered detector array module. The module body is formed of multiple non-conductive, thin film layers supporting a plurality of electronic devices. The module utilizes conductive patterns formed on the surface of a plurality of the layers to effect connections between and among electronic devices and external electronics. A detector array and an electrical interconnect may be joined to end portions of the module, in electrical communication with the layer conductive patterns. Transverse conductive connectors such as vias are provided within the module extending between the layers. Connections between and among the electronic devices and external electronics are thereby supported by transverse connections within the module and the electrical interconnect.

Abstract: An infrared detection module is disclosed for interfacing a plurality of detector elements to external electronics. The module is formed of a plurality of multi-channel integrated circuits stacked in substantially overlapping registry with adjacent integrated circuits separated by an insulating layer. Each integrated circuit is formed to have exposed conductive areas along first and second edge portions thereof. Each detector array segment is disposed transverse to the plane of the integrated circuits and connected to conductive areas on each integrated circuit along first edge portions thereof. A module header interface is disposed transverse to the plane of the integrated circuits and is electrically connected to the conductive areas along the integrated circuit second edge portions.

Abstract: On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.