Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.

Abstract: Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.

Abstract: Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.

Abstract: A coherency error detection and reporting mechanism monitors for coherency errors in a processor and between processors. When a requestor broadcasts a memory address in a command and a coherency error is detected, information regarding the command that caused the coherency error is logged, and the coherency error is reported a system error handler. The information logged for the coherency error may include the address of the coherency error, the requestor, the command, the response to the command, the scope of the coherency error, the error type, etc. Logging information relating to the coherency error provides more information to a person analyzing the processor for failures to more easily track down the cause of coherency errors.

Abstract: Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.

Abstract: A coherency error detection and reporting mechanism monitors for coherency errors in a processor and between processors. When a requestor broadcasts a memory address in a command and a coherency error is detected, information regarding the command that caused the coherency error is logged, and the coherency error is reported a system error handler. The information logged for the coherency error may include the address of the coherency error, the requestor, the command, the response to the command, the scope of the coherency error, the error type, etc. Logging information relating to the coherency error provides more information to a person analyzing the processor for failures to more easily track down the cause of coherency errors.

Abstract: A method for monitoring performance of events occurring in a multiprocessor system is provided where the performance monitoring units (PMUs) are globally synchronized. The global synchronization is carried out with a dedicated bit field set to any of pause, stop, restart, or reset command. The command is sent across the scan communications interface (SCOM) of all chips by using existing fabric connecting all nest units to control the PMUs in the system. A pre-scale counter before a main counter may be used to buffer event counts until a reset or a restart command is sent to the SCOM in the system.

Abstract: A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can continually increase a command rate of an interconnect if one or more requests to lower the command rate are not received within one or more periods of time. In one example, the command rate can be set to a fastest level. In another example, the command rate can be incrementally increased over periods of time. If a request to lower the command rate is received, the command rate can be set to a reference level or can be decremented to one slower rate level. In one or more embodiments, the one or more requests to lower the command rate can be based on at least one of an issue rate of speculative commands and a number of overcommit failures, among others.

Abstract: A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.

Abstract: A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.

Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.

Abstract: In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes; determine that a message indicating a dropped command, associated with the rate master command, is received; determine that a count, associated with dropped commands, satisfies a threshold; and provide, to the processing nodes via the interconnect, a signal indicating a command rate, in response to determining that the count satisfies the threshold. Moreover, the count can be incremented in response to determining that the message is received. The at least one of multiple processing nodes can receive, via the interconnect, the signal indicating the command rate and can utilize the command rate in issuing speculative commands, via the interconnect.