Patents by Inventor Charles Fuoco
Charles Fuoco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11509302Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: GrantFiled: October 26, 2020Date of Patent: November 22, 2022Assignee: Texas Instruments IncorporatedInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Patent number: 11212256Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.Type: GrantFiled: February 10, 2020Date of Patent: December 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
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Publication number: 20210044292Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Patent number: 10819334Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: GrantFiled: March 12, 2019Date of Patent: October 27, 2020Assignee: Texas Instruments IncorporatedInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Publication number: 20200304464Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.Type: ApplicationFiled: February 10, 2020Publication date: September 24, 2020Inventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
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Patent number: 10560428Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.Type: GrantFiled: August 17, 2017Date of Patent: February 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
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Publication number: 20190212794Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Patent number: 10228736Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.Type: GrantFiled: December 30, 2016Date of Patent: March 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Publication number: 20190058691Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
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Publication number: 20180189156Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Patent number: 9015376Abstract: A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.Type: GrantFiled: April 29, 2012Date of Patent: April 21, 2015Assignee: Texas Instruments IncorporatedInventors: Michael A. Denio, Brian Karguth, Akila Subramaniam, Charles Fuoco
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Patent number: 8706937Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: GrantFiled: December 17, 2011Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Publication number: 20130290984Abstract: A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.Type: ApplicationFiled: April 29, 2012Publication date: October 31, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael A. Denio, Brian Karguth, Akila Subramaniam, Charles Fuoco
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Publication number: 20130054852Abstract: Transaction requests in an interconnect fabric in a system with multiple nodes are managed in a manner that prevents deadlocks. One or more patterns of transaction requests from a master device to various slave devices within the multiple nodes that may cause a deadlock are determined. While the system is in operation, an occurrence of one of the patterns is detected by observing a sequence of transaction requests from the master device. A transaction request in the detected pattern is stalled to allow an earlier transaction request to complete in order to prevent a deadlock.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Inventors: Charles Fuoco, Akila Subramaniam
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Publication number: 20120226839Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events.Type: ApplicationFiled: January 11, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles Fuoco, Brian Cruickshank, Akila Subramaniam, Chunhua Hu, Samuel Paul Visalli
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Publication number: 20120226837Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.Type: ApplicationFiled: December 17, 2011Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian Cruickshank, David Quintin Bell, Samuel Paul Visalli, Chunhua Hu, Akila Subramaniam, Charles Fuoco
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Patent number: 6985982Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.Type: GrantFiled: October 24, 2001Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, David A. Comisky, Charles Fuoco, Raguram Damodaran
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Patent number: 6694385Abstract: The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.Type: GrantFiled: August 11, 2000Date of Patent: February 17, 2004Assignee: Texas Instruments IncorporatedInventors: Charles Fuoco, David A. Comisky, Sanjive Agarwala
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Patent number: 6594713Abstract: An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.Type: GrantFiled: August 11, 2000Date of Patent: July 15, 2003Assignee: Texas Instruments IncorporatedInventors: Charles Fuoco, David A. Comisky, Sanjive Agarwala, Raguram Damodaran
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Publication number: 20020078269Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.Type: ApplicationFiled: October 24, 2001Publication date: June 20, 2002Inventors: Sanjive Agarwala, David A. Comisky, Charles Fuoco, Raguram Damodaran