Patents by Inventor Charles Gardner

Charles Gardner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11980349
    Abstract: An endoscope has an improved chip-on-tip configuration that includes both a first configuration of source illumination fibers and a second plurality of source illumination fibers, along with a camera chip. The combination of the camera chip and the source illumination fibers on the tip of the endoscope results in endoscopes with reduced size and weight.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 14, 2024
    Assignee: CHEMIMAGE CORPORATION
    Inventors: Patrick Treado, Charles Gardner, Shona Stewart, Aaron Smith
  • Publication number: 20240095720
    Abstract: Automatic token wallet generation includes generating a token wallet generated for a unique identifier that is associated with a person. The unique identifier may be a communication identifier like an email address, a telephone number, a social media handle, and so on. Storage space may be allocated for the token wallet and may be associated with the unique identifier. One or more NFTs (non-fungible tokens) may then be associated with the token wallet. In some examples, the token wallet may be automatically created in response to a request to associate an NFT with it. In other examples, the token wallet may be created in response to a request to perform other actions related to the token wallet.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 21, 2024
    Inventors: Jeffrey Binder, Charles Hasek, Lindsay Gardner
  • Publication number: 20240070662
    Abstract: A non-fungible token (“NFT”) document platform includes a host platform that is operable to create and/or perform one or more transactions related to one or more NFTs on behalf of and/or for one or more other entities. Creation of the NFTs may involve creation of one or more smart contracts, storage of the smart contracts and/or the NFTs in one or more blockchains, and so on. The NFT document platform may also be operable to mint one or more documents, such as one or more birth certificates, contracts and other signed documents, titles, prescriptions, licenses and/or identification documents, checks, money, gift cards, and so on. The smart contracts and/or NFTs may correspond to the one or more minted documents. The NFTs may be usable to authenticate the minted documents, evidence ownership of the minted documents, control the ability to perform transactions regarding the minted documents, and so on.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Inventors: Jeffrey Binder, Charles Hasek, Lindsay Gardner
  • Publication number: 20240065113
    Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Geoffrey Charles GARDNER, Sergei Vyatcheslavovich GRONIN, Flavio GRIGGIO, Raymond Leonard KALLAHER, Noah Seth CLAY, Michael James MANFRA
  • Patent number: 11849639
    Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 19, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Sergei Vyatcheslavovich Gronin, Flavio Griggio, Raymond Leonard Kallaher, Noah Seth Clay, Michael James Manfra
  • Patent number: 11737374
    Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: August 22, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Sergei Vyacheslavovich Gronin, Geoffrey Charles Gardner
  • Patent number: 11619211
    Abstract: A pitch bearing for coupling a rotor blade to a hub of a wind turbine includes an outer race mountable to the hub and an inner race rotatable relative to the outer race and mountable to the rotor blade. The inner race is formed by first and second ring components, each of the first and second ring components having an outer annular face and an inner annular face. The first and second ring components are joined together at the inner annular faces such that the inner annular faces are opposed and opposite each other. A layer of friction enhancing material is inserted/disposed between the opposed inner annular faces, the friction enhancing material including an abrasive particulate component that increases a coefficient of friction to minimize slippage between the first and second ring components.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 4, 2023
    Assignee: General Electric Renovables Espana, S.L.
    Inventors: Gerard Iain Madden, Charles Gardner Bouchard, Jr., Elizabeth Marie Hood
  • Publication number: 20220311216
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 29, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. GRONIN, Geoffrey Charles GARDNER, Raymond Leonard KALLAHER
  • Patent number: 11362487
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. Gronin, Geoffrey Charles Gardner, Raymond Leonard Kallaher
  • Publication number: 20220149262
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: December 23, 2021
    Publication date: May 12, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Publication number: 20220136487
    Abstract: A pitch bearing for coupling a rotor blade to a hub of a wind turbine includes an outer race mountable to the hub and an inner race rotatable relative to the outer race and mountable to the rotor blade. The inner race is formed by first and second ring components, each of the first and second ring components having an outer annular face and an inner annular face. The first and second ring components are joined together at the inner annular faces such that the inner annular faces are opposed and opposite each other. A layer of friction enhancing material is inserted/disposed between the opposed inner annular faces, the friction enhancing material including an abrasive particulate component that increases a coefficient of friction to minimize slippage between the first and second ring components.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Gerard Iain Madden, Charles Gardner Bouchard, JR., Elizabeth Marie Hood
  • Patent number: 11211543
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Patent number: 11201273
    Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Igorevich Pikulin, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Georg Wolfgang Winkler, Sergei Vyatcheslavovich Gronin, Peter Krogstrup Jeppesen, Michael James Manfra, Andrey Antipov, Roman Mykolayovych Lutchyn
  • Publication number: 20210376572
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. GRONIN, Geoffrey Charles GARDNER, Raymond Leonard KALLAHER
  • Patent number: 11147416
    Abstract: A framework for constructing free-standing counters includes opposed, rectangular first and second end frames, each having an inner face and an opposed outer face, as well as opposed, rectangular front and rear frames, each having oppositely- and outwardly-directed first and second ends. The first ends of the front and rear frames are each coupled to the inner face of the first end frame, and the second ends of the front and rear frames are each coupled to the inner face, to form a box structure having a top and an opposed bottom. The framework also includes ties which extend transversely from the first and second end frames to the front and rear frames. A leg is coupled to each tie for adjustment to extend below the bottom of the box structure.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 19, 2021
    Inventor: William Charles Gardner
  • Publication number: 20210257537
    Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.
    Type: Application
    Filed: April 7, 2021
    Publication date: August 19, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Sergei Vyacheslavovich Gronin, Geoffrey Charles Gardner
  • Publication number: 20210175408
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: February 20, 2020
    Publication date: June 10, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Publication number: 20210126181
    Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Georg Wolfgang Winkler, Roman Mykolayovych Lutchyn, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Sergei Vyatcheslavovich Gronin, Michael James Manfra, Farhad Karimi
  • Publication number: 20210106174
    Abstract: A framework for constructing free-standing counters includes opposed, rectangular first and second end frames, each having an inner face and an opposed outer face, as well as opposed, rectangular front and rear frames, each having oppositely- and outwardly-directed first and second ends. The first ends of the front and rear frames are each coupled to the inner face of the first end frame, and the second ends of the front and rear frames are each coupled to the inner face, to form a box structure having a top and an opposed bottom. The framework also includes ties which extend transversely from the first and second end frames to the front and rear frames. A leg is coupled to each tie for adjustment to extend below the bottom of the box structure.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 15, 2021
    Inventor: William Charles Gardner
  • Patent number: D931467
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: September 21, 2021
    Assignee: RDS
    Inventors: George Stefan Golda, Sam Eletr, Bruce O'Neil, Juan Carlos Beltran, Robert Charles Gardner