Patents by Inventor Charles Guo Lin
Charles Guo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962233Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: GrantFiled: May 1, 2023Date of Patent: April 16, 2024Assignee: Skyworks Solutions, Inc.Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick Johannus De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Publication number: 20230387782Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: May 1, 2023Publication date: November 30, 2023Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick Johannus De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
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Patent number: 11575305Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: GrantFiled: October 8, 2020Date of Patent: February 7, 2023Assignee: Skyworks Solutions, Inc.Inventors: Michael R. May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamás Marozsák, András V. Horváth
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Publication number: 20220115941Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Michael R. May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamás Marozsák, András V. Horváth
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Patent number: 10699995Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.Type: GrantFiled: May 9, 2018Date of Patent: June 30, 2020Assignee: Silicon Laboratories Inc.Inventors: Michael R. May, Charles Guo Lin, Carlos Briseno-Vidrios
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Publication number: 20190348355Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.Type: ApplicationFiled: May 9, 2018Publication date: November 14, 2019Inventors: Michael R. May, Charles Guo Lin, Carlos Briseno-Vidrios
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Patent number: 8552797Abstract: In an RC calibration circuit, a single reference current is used to generate voltages across both a resistive and capacitive element. The component value of one of the resistive and capacitive element is successively altered until the voltages are substantially equal. Additionally, parasitic capacitances in the circuit are precharged to the resistive element voltage prior to the comparison. The RC calibration circuit eliminates the errors due to current matching and parasitic capacitances in prior art calibration circuits. The circuit includes a comparator and a digital control circuit (DCW) including a successive approximation register (SAR) holding the value of the digital control word used to control the component value of the tunable resistive or capacitive element. The SAR alters the DCW in an iterative, bit-by-bit binary searching pattern in response to the comparator output.Type: GrantFiled: December 21, 2011Date of Patent: October 8, 2013Assignee: ST-Ericsson SAInventor: Charles Guo Lin
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Publication number: 20130033307Abstract: In an RC calibration circuit, a single reference current is used to generate voltages across both a resistive and capacitive element. The component value of one of the resistive and capacitive element is successively altered until the voltages are substantially equal. Additionally, parasitic capacitances in the circuit are precharged to the resistive element voltage prior to the comparison. The RC calibration circuit eliminates the errors due to current matching and parasitic capacitances in prior art calibration circuits. The circuit includes a comparator and a digital control circuit (DCW) including a successive approximation register (SAR) holding the value of the digital control word used to control the component value of the tunable resistive or capacitive element. The SAR alters the DCW in an iterative, bit-by-bit binary searching pattern in response to the comparator output.Type: ApplicationFiled: December 21, 2011Publication date: February 7, 2013Inventor: Charles Guo Lin