Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an interlayer dielectric layer. A plurality of parallel conductive lines is in the interlayer dielectric layer. The plurality of parallel conductive lines includes a first conductive line and a second conductive line. The first conductive line includes breaks therein with first and second dielectric plugs separating portions of the first conductive line, one of the portions between the first dielectric plug and the second dielectric plug and having a first dimension. The second conductive line includes first and second conductive line portions separated by an intervening conductive via structure, the conductive via structure separated from the first and second conductive line portions, and the conductive via structure having a second dimension parallel with the first dimension, the second dimension less than the first dimension.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a fin with a first end and a second end. In an embodiment, a first dielectric covers the first end of the fin, and a second dielectric covers the second end of the fin. In an embodiment, a gate structure is over the first end of the fin, where the gate structure is on a top surface of the fin and a top surface of the first dielectric.

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure.

Abstract: A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

Abstract: Described herein are integrated circuit structures having versatile channel placement, and methods of fabricating integrated circuit structures having versatile channel placement. In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is immediately neighboring and parallel with the first vertical stack of horizontal nanowires and has a second width greater than the first width. A third vertical stack of horizontal nanowires is immediately neighboring and parallel with the second vertical stack of horizontal nanowires and has the first width.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a directed bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. A gate stack is over and around the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein at least one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

Abstract: Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

Abstract: Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.

Abstract: Integrated circuit structures having backside self-aligned conductive pass-through contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive pass-through contacts, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A dummy gate electrode is laterally between the first stack of nanowires and the second stack of nanowires. A conductive pass-through contact is laterally between the first stack of nanowires and the second stack of nanowires. The conductive pass-through contact is on and in contact with the dummy gate electrode.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a backside removal approach, are described. For example, an integrated circuit structure includes a first insulator sub-fin structure over a first stack of nanowires. A second insulator sub-fin structure is over a second stack of nanowires, the second stack of nanowires having a greater number of nanowires than the first stack of nanowires, and the second insulator sub-fin structure having a vertical thickness less than a vertical thickness of the first insulator sub-fin structure. A first gate electrode is around the first stack of nanowires, and a second gate electrode is around the second stack of nanowires.