Abstract: A data storage system includes a non-volatile memory array controlled by a controller. In response to receipt of write data to be written to the non-volatile memory array, the controller determines whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the block. In response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the candidate block and programming an alternative block with the write data.

Abstract: In a data storage system, a data set as compressed by a first compression technique (e.g., a hardware-based compression technique) is stored in non-volatile data storage in association with at least a particular address. In response to a subsequent garbage collection read of the particular address, control logic determines whether or not to compress the data set with a second compression technique (e.g., a software-based compression technique). In response to determining not to compress the data set with the second compression technique, the control logic writes the data set back to the non-volatile data storage as compressed by the first compression technique. In response to determining to compress the data set with the second compression technique, the control logic compresses the data set with the second compression technique and writes the data set back to the non-volatile data storage as compressed by the second compression technique.

Abstract: Read errors following programming in a multi-level non-volatile memory are mitigated by a controller of the non-volatile memory. The controller temporarily buffers, in a cache, pages of data programmed into the non-volatile memory. In response to receiving a read request for a target page of data programmed into the non-volatile memory, where the read request is received during a delay time affecting the target page, the controller services the read request by accessing data of the target page in the cache in response to the read request hitting in the cache. The controller instead services the read request from the non-volatile memory in response to the read request missing in the cache. When servicing the read request from the non-volatile memory, the controller preferably reads the target page from the non-volatile memory utilizing a set of read voltage thresholds determined based on the read-after-write delay.

Abstract: A method, according to one embodiment, includes assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, and writing the data streams in parallel to page-stripes having a same index across a series of planes of memory. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A storage system includes a controller connected to a solid state memory device. The controller releases the physical address for reassignment when no pending reads are associated with the physical address. In certain embodiments, a read status table may be included within the storage system. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A data storage system includes a controller, a hot spare storage device and a plurality of primary storage devices. The controller utilizes the hot spare storage device to mirror only a subset of each stripe of logical pages written across the data storage array, where the subset includes a logical page determined by a write input/output operation (IOP) policy. In response to receipt of a write IOP, the controller writes a stripe including a plurality of logical data pages and a logical data protection page across the plurality of primary storage devices and mirrors the logical page determined by the write IOP policy on the hot spare storage device. In response to a failure of a storage device among the plurality of primary storage devices, contents of the failed storage device not already mirrored on the hot spare storage device are rebuilt on the hot spare storage device.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: According to one embodiment, a method includes assigning a subset of physical pages within a block of non-volatile memory to a pseudo-physical block, wherein a number of pages in the pseudo-physical block is less than a number of physical pages within the non-volatile memory block, and reassigning physical pages within the block of non-volatile memory to the pseudo-physical block upon occurrence of an event. The assigning includes: determining a health metric for each of the physical pages within the block of non-volatile memory, and selecting a subset of the physical pages for assignment to the pseudo-physical block based on the health metric. Moreover, the subset of pages has a fixed size for at least a number of reassignments.

Abstract: Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.

Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: A mechanism is provided in a non-volatile memory controller for reducing read access latency by straddling pages across non-volatile memory channels. Responsive to a request to write a logical page to a non-volatile memory array, the non-volatile memory controller determines whether the logical page fits into a current physical page. Responsive to determining the logical page does not fit into the current physical page, the non-volatile memory controller writes a first portion of the logical page to a first physical page in a first block and writes a second portion of the logical page to a second physical page in a second block. The first physical page and the second physical page are on different non-volatile memory channels.

Abstract: A controller-implemented method, according to one embodiment, includes: examining, by the controller, each of a plurality of journal entries from at least one journal beginning with a most recent one of the journal entries in a most recent one of the at least one journal and working towards an oldest one of the journal entries in an oldest one of the at least one journal, the journal entries corresponding to one or more updates made to one or more logical to physical table (LPT) entries of a LPT; determining, by the controller, whether a current LPT entry, which corresponds to a currently examined journal entry, has already been updated; and discarding, by the controller, the currently examined journal entry in response to determining that the current LPT entry has already been updated.

Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.

Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.

Abstract: A controller-implemented method, according to one embodiment, includes: restoring a valid snapshot of a LPT from the non-volatile random access memory, examining each journal entry from at least one journal beginning with a most recent one of the journal entries in a most recent one of the at least one journal and working towards an oldest one of the journal entries in an oldest one of the at least one journal, the journal entries corresponding to updates made to one or more entries of the LPT, determining whether a current LPT entry which corresponds to a currently examined journal entry has already been updated, using the currently examined journal entry to update the current LPT entry in response to determining that the current LPT entry has not already been updated, and discarding the currently examined journal entry in response to determining that the current LPT entry has already been updated.

Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.