Abstract: A high density integrated circuit module is comprised of a plurality of integrated circuit chips; each of the chips has top and bottom surfaces and thin sides; and all of the chips are arranged in a stack in which the sides of the chips form multiple faces of the stack. Also, in accordance with the invention, a selected face of the stack has a zigzag shape which exposes a portion of the top surface of each chip on that face; and, bonding pads for carrying input/output signals to/from the chips are located on the exposed top surface portion of the chips. This zigzag shape is produced by (a) providing an indentation in the side of each of the chips which lie along the selected stack face; or (b) by offsetting the sides of the chps from each other as they lie along the selected stack face; or (c) by providing respective spacers between the chips and indenting them from the chips along the selected stack face.

Abstract: A controller for controlling access to a plurality of records that can be accessed and changed by several independent processors comprises: a plurality of flip-flops corresponding in number to the plurality of records with each flip-flop representing a particular record; a circuit for receiving a programmable control word from any of the processors which identifies multiple records of which access is sought; a circuit for selecting in parallel and logically ANDing output signals from all of those flip-flops which correspond to the identified records; a circuit for sending a signal, if the ANDing operation yields a logical ONE, to the processor which sent the control word signaling that it may access and change the identified records; a circuit for setting in parallel via a single pulse all of those flip-flops which correspond to the identified records if the ANDing operation yields a logical ONE; and a circuit for storing the control word if the ANDing operation yields a logical ZERO.

Abstract: A method and apparatus for increasing access speed in a random access memory comprising the utilization of a prefetch register for receiving and temporarily storing a first address portion representing the location of a group of words stored in memory. The first address portion is subsequently utilized to access memory to retrieve a group of words to be stored in memory output registers; a second address portion is utilized to select words contained in the output registers of the memory. Several second address portions may address the various words stored in the output registers of the memory while the first address portion remains the same.

Abstract: The disclosed random access memory (RAM) for digital data includes the normal data input circuit, a memory matrix for storing applied data, address control circuits for selectively addressing any cell of the memory matrix, and a data output circuit for selectively applying digital data stored in the memory matrix to a data output line. To achieve a high digital data output rate, a rate substantially higher than the rate at which the cells of the memory can be addressed, the improved RAM includes a data output register having a multiplicity of data storage elements and means for simultaneously reading digital data stored in the memory matrix in parallel into the data storage elements of the output register. This data then is selectively applied to the data output line while new data is being addressed in the memory matrix.

Abstract: Apparatus in a high-density disk storage controller for qualitatively testing circuits recovering self-clocking data, on-line and independently of any storage device. The ability of the data recovery apparatus, which is designed with broad-tolerance circuits and components, to recover a data pattern having predetermined and worst-case phase-shift or jitter is tested dynamically under microprocessor control. The test results are evaluated and apparatus in the data recovery circuits selectively positions a read strobe precisely in the center of the data window to compensate for variations of delay encountered in different combinations of the broad-parameter components.

Abstract: Apparatus for generating self-clocking data of a predetermind format simulating control information recorded on a dynamic magnetic medium storage device. The data generator includes means for simulating servo clock signals and encoding means for producing formatted data signals having jitter and phase relationship to the servo signals which are worst-case rather than random. The apparatus is utilized to test data recovery circuits independently of the storage device.